PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 127

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.6.3
Figure 8-3
mode. This mode allows table write operations to
word-wide external memories with byte selection
capability. This generally includes both word-wide
Flash and SRAM devices.
During a TBLWT cycle, the TABLAT data is presented
on the upper and lower byte of the AD<15:0> bus. The
WRH signal is strobed for each write cycle; the WRL
pin is not used. The BA0 or UB/LB signals are used to
select the byte to be written, based on the Least
Significant bit of the TBLPTR register.
FIGURE 8-3:
 2009-2011 Microchip Technology Inc.
Note 1:
PIC18F87K22
2:
3:
shows an example of 16-Bit Byte Select
16-BIT BYTE SELECT MODE
A<19:16>
AD<15:8>
AD<7:0>
This signal only applies to table writes. See
Upper order address lines are used only for 20-bit address width.
Demultiplexing is only required when multiple memory devices are accessed.
WRH
WRL
ALE
BA0
OE
UB
I/O
LB
(2)
16-BIT BYTE SELECT MODE EXAMPLE
373
373
Section 7.1 “Table Reads and Table
A<20:1>
A<20:1>
PIC18F87K22 FAMILY
138
Flash and SRAM devices use different control signal
combinations to implement Byte Select mode. JEDEC
standard Flash memories require that a controller I/O
port pin be connected to the memory’s BYTE/WORD
pin to provide the select signal. They also use the BA0
signal from the controller as a byte address. JEDEC
standard static RAM memories, on the other hand, use
the UB or LB signals to select the byte.
(3)
A<x:1>
A<x:1>
CE
UB
A0
BYTE/WORD
CE
LB
OE WR
SRAM Memory
Writes”.
Flash Memory
Address Bus
Data Bus
Control Lines
JEDEC Word
JEDEC Word
(1)
OE WR
D<15:0>
D<15:0>
DS39960D-page 127
(1)
D<15:0>
D<15:0>