PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 174

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

corresponding Data Direction and Output Latch registers
PIC18F87K22 FAMILY
12.4
PORTC is an eight-bit wide, bidirectional port. The
are TRISC and LATC. Only PORTC pins, RC2 through
RC7, are digital only pins.
PORTC is multiplexed with ECCP, MSSP and EUSART
peripheral functions
Schmitt Trigger input buffers. The pins for ECCP, SPI
and EUSART are also configurable for open-drain out-
put whenever these functions are active. Open-drain
configuration is selected by setting the SPIOD,
CCPxOD and U1OD control bits in the registers,
ODCON1 and ODCON3.
RC1 is normally configured as the default peripheral
pin for the ECCP2 module. The assignment of ECCP2
is controlled by Configuration bit, CCP2MX (default
state, CCP2MX = 1).
TABLE 12-5:
DS39960D-page 174
RC0/SOSCO/
SCLKI/
RC1/SOSCI/
ECCP2/P2A
RC2/ECCP1/
P1A
Legend:
Note 1:
Pin Name
PORTC, TRISC and
LATC Registers
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, TTL = TTL Buffer Input,
I
Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
2
C = I
Function
ECCP2
SOSCO
ECCP1
SOSCI
SCLKI
2
RC0
RC1
RC2
PORTC FUNCTIONS
P2A
P1A
C™/SMBus Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
(1)
(Table
Setting
TRIS
0
1
1
1
0
1
x
0
1
0
0
1
0
1
0
12-5). The pins have
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
Type
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
LATC<0> data output.
PORTC<0> data input.
SOSC oscillator output.
Digital clock input; enabled when SOSC oscillator is disabled.
LATC<1> data output.
PORTC<1> data input.
SOSC oscillator input.
ECCP2 compare output and ECCP2 PWM output; takes priority over port data.
ECCP2 capture input.
ECCP2 Enhanced PWM output, Channel A.
May be configured for tri-state during Enhanced PWM shutdown events; takes
priority over port data.
LATC<2> data output.
PORTC<2> data input.
ECCP1 compare output and ECCP1 PWM output; takes priority over port data.
ECCP1 capture input.
ECCP1 Enhanced PWM output, Channel A.
May be configured for tri-state during Enhanced PWM shutdown events; takes
priority over port data.
When enabling peripheral functions, use care in defin-
ing TRIS bits for each PORTC pin. Some peripherals
can override the TRIS bit to make a pin an output or
input. Consult the corresponding peripheral section for
the correct TRIS bit settings.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 12-3:
CLRF
CLRF
MOVLW
MOVWF
Note:
PORTC
LATC
0CFh
TRISC
These pins are configured as digital inputs
on any device Reset.
Description
 2009-2011 Microchip Technology Inc.
; Initialize PORTC by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
INITIALIZING PORTC