PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 62

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

primary clock is providing the device clocks. The IDLEN
PIC18F87K22 FAMILY
4.3
The power-managed Sleep mode in the PIC18F87K22
family of devices is identical to the legacy Sleep mode
offered in all other PIC devices. It is entered by clearing
the IDLEN bit (the default state on device Reset) and
executing the SLEEP instruction. This shuts down the
selected oscillator
bits are cleared.
Entering Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the LF-INTOSC source will continue
to operate. If the SOSC oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS<1:0> bits
becomes ready (see
will be clocked from the internal oscillator block if either
the Two-Speed Start-up or the Fail-Safe Clock Monitor is
enabled (see
CPU”). In either case, the OSTS bit is set when the
and SCS bits are not affected by the wake-up.
FIGURE 4-5:
FIGURE 4-6:
DS39960D-page 62
Peripheral
Program
Counter
Note 1: T
OSC1
Sleep
Clock
Clock
CPU
CPU Clock
PLL Clock
Peripheral
Program
Sleep Mode
Counter
Output
OSC1
Clock
Q1
Section 28.0 “Special Features of the
OST
Q2
PC
= 1024 T
(Figure
Q3
Figure
Wake Event
Q4
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q1
OSC
4-5). All clock source status
4-6). Alternately, the device
Q1
; T
T
OST
PLL
(1)
= 2 ms (approx). These intervals are not shown to scale.
PC
T
PLL (1)
OSTS bit Set
Q2 Q3 Q4 Q1 Q2
PC + 2
4.4
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS<1:0> bits. The CPU,
however, will not be clocked. The clock source status bits
are not affected. This approach is a quick method to
switch from a given Run mode to its corresponding Idle
mode.
If the WDT is selected, the LF-INTOSC source will
continue to operate. If the SOSC oscillator is enabled,
it will also continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of T
(Parameter 38,
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or Sleep mode, a WDT time-
out will result in a WDT wake-up to the Run mode
currently specified by the SCS<1:0> bits.
PC + 2
Idle Modes
Q3 Q4 Q1 Q2
Table
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PC + 4
31-13) while it becomes ready to
Q3 Q4
Q1 Q2 Q3 Q4
PC + 6
CSD