PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 410

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
REGISTER 28-6:
DS39960D-page 410
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
MCLRE
R/P-1
2:
Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘ 0 ’.
Not implemented on 32K devices (PIC18F65K22 and PIC18F85K22).
MCLRE: MCLR Pin Enable bit
1 = MCLR pin is enabled; RG5 input pin is disabled
0 = RG5 input pin is enabled; MCLR is disabled
Unimplemented: Read as ‘ 0 ’
MSSPMSK: MSSP V3 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode is enabled
0 = 5-Bit Address Masking mode is enabled
Unimplemented: Read as ‘ 0 ’
ECCPMX: ECCP MUX bit
1 =
0 =
CCP2MX: ECCP2 MUX bit
1 = ECCP2 is multiplexed with RC1
0 = ECCP2 is multiplexed with RB3 in Extended Microcontroller mode; ECCP2 is multiplexed with
- ECCP1 (P1B/P1C) is multiplexed onto RE6 and RE5, CCP6 onto RE6, and CCP7 onto RE5
- ECCP3 (P3B/P3C) is multiplexed onto RE4 and RE3, CCP8 onto RE4, and CCP9 onto RE3
- ECCP1 (P1B/P1C) is multiplexed onto RH7 and RH6, CCP6 onto RH7, and CCP7
- ECCP3 (P3B/P3C) is multiplexed onto RH5 and RH4, CCP8 onto RH5, and CCP9
RE7 in Microcontroller mode
U-0
—
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
P = Programmable bit
W = Writable bit
‘1’ = Bit is set
U-0
—
(1)
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
MSSPMSK
R/P-1
U-0
—
 2009-2011 Microchip Technology Inc.
x = Bit is unknown
ECCPMX
R/P-1
(1)
(2)
(2)
CCP2MX
onto RH6
onto RH4
R/P-1
bit 0