PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 419

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

28.2
For the PIC18F87K22 family of devices, the WDT is
driven by the LF-INTOSC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
LF-INTOSC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in
Configuration Register 2H. Available periods range
from 4 ms to 4,194 seconds (about one hour). The
WDT and postscaler are cleared when any of the
following events occur: a SLEEP or CLRWDT instruction
is executed, the IRCF bits (OSCCON<6:4>) are
changed or a clock failure has occurred.
FIGURE 28-1:
 2009-2011 Microchip Technology Inc.
WDT Disabled in Hardware,
Device is Active, Disabled
WDT Enabled only while
WDTEN1
WDTEN0
Watchdog Timer (WDT)
WDT Controlled with
SWDTEN bit Setting
Change on IRCF bits
SWDTEN Disabled
SWDTEN Disabled
All Device Resets
WDT Enabled,
INTRC Source
WDTPS<3:0>
CLRWDT
WDT BLOCK DIAGRAM
Sleep
Enable WDT
WDT Counter
 128
4
Programmable Postscaler
PIC18F87K22 FAMILY
The WDT can be operated in one of four modes as
determined by the WDTEN<1:0> (CONFIG2H<1:0>
bits. The four modes are:
• WDT Enabled
• WDT Disabled
• WDT under Software Control,
• WDT
1:1 to 1:1,048,576
SWDTEN (WDTCON<0>)
- Enabled during normal operation
- Disabled during Sleep
Note 1: The CLRWDT and SLEEP instructions
2: Changing the setting of the IRCF bits
3: When a CLRWDT instruction is executed,
clear the WDT and postscaler counts
when executed.
(OSCCON<6:4>) clears the WDT and
postscaler counts.
the postscaler count will be cleared.
INTRC Source
WDTEN<1:0>
SWDTEN
Reset
DS39960D-page 419
Wake-up from
Power-Managed
Modes
Enable WDT
WDT
Reset