PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 229

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PIC18F67K22-I/MR

Manufacturer Part Number
PIC18F67K22-I/MR
Description
128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet

Specifications of PIC18F67K22-I/MR

Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F67K22-I/MRRSL
Manufacturer:
FSC
Quantity:
250
18.1.1
REGISTER 18-1:
 2009-2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Note 1:
RTCEN
R/W-0
2:
3:
4:
(2)
The RTCCFG register is only affected by a POR.
A write to the RTCEN bit is only allowed when RTCWREN = 1.
This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.
RTCWREN can only be written with the unlock sequence (see
RTCC CONTROL REGISTERS
RTCEN: RTCC Enable bit
1 = RTCC module is enabled
0 = RTCC module is disabled
Unimplemented: Read as ‘0’
RTCWREN: RTCC Value Registers Write Enable bit
1 = RTCVALH and RTCVALL registers can be written to by the user
0 = RTCVALH and RTCVALL registers are locked out from being written to by the user
RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTCVALH, RTCVALL and ALRMRPT registers can change while reading if a rollover ripple
0 = RTCVALH, RTCVALL and ALCFGRPT registers can be read without concern over a rollover
HALFSEC: Half-Second Status bit
1 = Second half period of a second
0 = First half period of a second
RTCOE: RTCC Output Enable bit
1 = RTCC clock output is enabled
0 = RTCC clock output is disabled
RTCPTR<1:0>: RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL
registers. The RTCPTR<1:0> value decrements on every read or write of RTCVALH<15:8> until it
reaches ‘00’.
RTCVALH:
00 = Minutes
01 = Weekday
10 = Month
11 = Reserved
RTCVALL:
00 = Seconds
01 = Hours
10 = Day
11 = Year
results in an invalid data read. If the register is read twice and results in the same data, the data
can be assumed to be valid.
ripple
U-0
RTCCFG: RTCC CONFIGURATION REGISTER
RTCWREN
W = Writable bit
‘1’ = Bit is set
R/W-0
(4)
(
2
)
RTCSYNC HALFSEC
R-0
(3)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F87K22 FAMILY
R-0
(4)
(3)
Example
(1)
RTCOE
R/W-0
18-1).
x = Bit is unknown
RTCPTR1
R/W-0
DS39960D-page 229
RTCPTR0
R/W-0
bit 0

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