PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 210

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
15.2
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) provides
the input for the 4-bit output counter/postscaler. This
counter generates the TMR2 match interrupt flag, which
is latched in TMR2IF (PIR1<1>). The interrupt is enabled
by setting the TMR2 Match Interrupt Enable bit, TMR2IE
(PIE1<1>).
A range of 16 postscaler options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0> (T2CON<6:3>).
FIGURE 15-1:
TABLE 15-1:
DS39960D-page 210
INTCON
PIR1
PIE1
IPR1
TMR2
T2CON
PR2
PMD1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Name
T2OUTPS<3:0>
T2CKPS<1:0>
F
OSC
/4
Timer2 Interrupt
Timer2 Register
Timer2 Period Register
GIE/GIEH
PSPMD
PSPIF
PSPIE
PSPIP
Bit 7
—
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
TIMER2 BLOCK DIAGRAM
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
PEIE/GIEL
CTMUMD
Internal Data Bus
1:1, 1:4, 1:16
2
Prescaler
ADIE
ADIP
ADIF
Bit 6
RTCCMD
TMR0IE
RC1IE
RC1IP
RC1IF
Bit 5
4
TMR2
Reset
8
TMR4MD
INT0IE
TX1IF
TX1IE
TX1IP
Bit 4
15.3
The unscaled output of TMR2 is available primarily to
the ECCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can optionally be used as the shift clock source
for the MSSP modules operating in SPI mode.
Additional information is provided in
“Master Synchronous Serial Port (MSSP)
Comparator
1:1 to 1:16
Postscaler
TMR3MD
SSP1IF
SSP1IE
SSP1IP
RBIE
Bit 3
8
TMR2/PR2
Match
Timer2 Output
TMR1GIF
TMR1GIE
TMR1GIP
TMR2MD
TMR2ON
TMR0IF
 2009-2011 Microchip Technology Inc.
Bit 2
PR2
8
T2CKPS1
TMR1MD
TMR2IF
TMR2IE
TMR2IP
INT0IF
Bit 1
Set TMR2IF
TMR2 Output
(to PWM or MSSPx)
Section 21.0
T2CKPS0
EMBDM
TMR1IF
TMR1IE
TMR1IP
Module”.
RBIF
Bit 0