PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 203

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.7
If ECCP modules are configured to use Timer1 and to
generate a Special Event Trigger in Compare mode
(CCPxM<3:0> = 1011), this signal will reset Timer1. The
trigger from ECCP2 will also start an A/D conversion, if
the A/D module is enabled. (For more information, see
Section 20.3.4 “Special Event
To take advantage of this feature, the module must be
configured as either a timer or a synchronous counter.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a period register for Timer1.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
Special Event Trigger, the write operation will take
precedence.
14.8
Timer1 can be configured to count freely or the count can
be enabled and disabled using the Timer1 gate circuitry.
This is also referred to as Timer1 gate count enable.
Timer1 gate can also be driven by multiple selectable
sources.
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Note:
Resetting Timer1 Using the ECCP
Special Event Trigger
Timer1 Gate
The Special Event Trigger from the
ECCPx module will only clear the TMR1
register’s content, but not set the TMR1IF
interrupt flag bit (PIR1<0>).
Trigger”.)
PIC18F87K22 FAMILY
14.8.1
The Timer1 Gate Enable mode is enabled by setting
the TMR1GE bit of the T1GCON register. The polarity
of the Timer1 Gate Enable mode is configured using
the T1GPOL bit (T1GCON<6>).
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See
TABLE 14-3:
† The clock on which TMR1 is running. For more
T1CLK
Note:
information, see




(†)
TIMER1 GATE COUNT ENABLE
The CCP and ECCP modules use Timers,
1 through 8, for some modes. The assign-
ment of a particular timer to a CCP/ECCP
module is determined by the Timer to CCP
enable bits in the CCPTMRSx registers.
For more details, see
Register 19-3
(T1GCON<6>)
T1GPOL
TIMER1 GATE ENABLE
SELECTIONS
0
0
1
1
Figure 14-4
Figure
and
14-1.
T1G Pin
Register
for timing details.
0
1
0
1
DS39960D-page 203
Counts
Holds Count
Holds Count
Counts
Register
20-2.
Operation
Timer1
19-2,