PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 19

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 1-3:
 2009-2011 Microchip Technology Inc.
RD0/PSP0/CTPLS
RD1/PSP1/T5CKI/T7G
RD2/PSP2
RD3/PSP3
RD4/PSP4/SDO2
RD5/PSP5/SDI2/SDA2
RD6/PSP6/SCK2/SCL2
RD7/PSP7/SS2
Legend: TTL = TTL compatible input
Note 1:
RD0
PSP0
CTPLS
RD1
PSP1
T5CKI
T7G
RD2
PSP2
RD3
PSP3
RD4
PSP4
SDO2
RD5
PSP5
SDI2
SDA2
RD6
PSP6
SCK2
SCL2
RD7
PSP7
SS2
2:
3:
4:
Pin Name
(4)
ST = Schmitt Trigger input with CMOS levels
I
P
I
Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
Not available on PIC18F65K22 and PIC18F85K22 devices.
The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit
(CONFIG3H<1>).
2
C = I
= Input
= Power
PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)
2
C™/SMBus
Pin Number Pin
QFN/TQFP
58
55
54
53
52
51
50
49
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
Buffer
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
—
2
2
C
C
PORTD is a bidirectional I/O port.
PIC18F87K22 FAMILY
Digital I/O.
Parallel Slave Port data.
CTMU pulse generator output.
Digital I/O.
Parallel Slave Port.
Timer5 clock input.
Timer7 external clock gate input.
Digital I/O.
Parallel Slave Port.
Digital I/O.
Parallel Slave Port.
Digital I/O.
Parallel Slave Port.
SPI data out.
Digital I/O.
Parallel Slave Port.
SPI data in.
I
Digital I/O.
Parallel Slave Port.
Synchronous serial clock.
Synchronous serial clock I/O for I
Digital I/O.
Parallel Slave Port.
SPI slave select input.
2
C™ data I/O.
CMOS = CMOS compatible input or output
Analog = Analog input
O
OD
= Output
= Open-Drain (no P diode to V
Description
2
C mode.
DS39960D-page 19
DD
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