PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 322

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
21.4.17.1
During a Start condition, a bus collision occurs if:
a)
b)
During a Start condition, both the SDAx and the SCLx
pins are monitored.
If the SDAx pin is already low, or the SCLx pin is
already low, then all of the following occur:
• The Start condition is aborted
• The BCLxIF flag is set
• The MSSP module is reset to its inactive state
The Start condition begins with the SDAx and SCLx
pins deasserted. When the SDAx pin is sampled high,
the
SSPxADD<6:0> and counts down to 0. If the SCLx pin
is sampled low while SDAx is high, a bus collision
occurs because it is assumed that another master is
attempting to drive a data ‘1’ during the Start condition.
FIGURE 21-28:
DS39960D-page 322
(Figure
SDAx
SCLx
SEN
BCLxIF
S
SSPxIF
SDAx or SCLx is sampled low at the beginning
of the Start condition
SCLx is sampled low before SDAx is asserted
low
Baud
(Figure
21-28)
Bus Collision During a Start
Condition
Rate
21-29).
Set SEN, Enable Start
Condition if SDAx = 1, SCLx = 1
Generator
BUS COLLISION DURING START CONDITION (SDAx ONLY)
(Figure
SDAx Sampled Low Before
Start Condition, Set BCLxIF,
S bit and SSPxIF Set Because
SDAx = 0, SCLx = 1
21-28).
SDAx Goes Low Before the SEN bit is Set.
Set BCLxIF,
S bit and SSPxIF Set Because
SDAx = 0, SCLx = 1
is
loaded
from
SSPxIF and BCLxIF are
Cleared in Software
If the SDAx pin is sampled low during this count, the
BRG is reset and the SDAx line is asserted early
(Figure
SDAx pin, the SDAx pin is asserted low at the end of
the BRG count. The Baud Rate Generator is then
reloaded and counts down to 0. If the SCLx pin is
sampled as ‘0’ during this time, a bus collision does not
occur. At the end of the BRG count, the SCLx pin is
asserted low.
Note:
SEN Cleared Automatically Because of Bus Collision,
MSSP module Reset into Idle State
21-30). If, however, a ‘1’ is sampled on the
The reason that a bus collision is not a
factor during a Start condition is that no two
bus masters can assert a Start condition at
the exact same time. Therefore, one
master will always assert SDAx before the
other. This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SSPxIF and BCLxIF are
Cleared in Software
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