PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 165

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.0
Depending on the device selected and features
enabled, there are up to nine ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three memory mapped registers for its
operation:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
• LAT register (Output Latch register)
Reading the PORT register reads the current status of
the pins, whereas writing to the PORT register writes to
the Output Latch (LAT) register.
Setting a TRIS bit (= 1) makes the corresponding port
pin an input (putting the corresponding output driver in
a High-Impedance mode). Clearing a TRIS bit (= 0)
makes the corresponding port pin an output (i.e., puts
the contents of the corresponding LAT bit on the
selected pin).
The Output Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving. Read-modify-write operations on the
LAT register read and write the latched output value for
the PORT register.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in
FIGURE 12-1:
 2009-2011 Microchip Technology Inc.
device)
RD LAT
Data
Bus
WR LAT
or PORT
WR TRIS
RD TRIS
RD PORT
I/O PORTS
TRIS Latch
Data Latch
CKx
CKx
D
D
GENERIC I/O PORT
OPERATION
Q
Q
Q
EN
EN
D
Figure
Input
Buffer
I/O Pin
12-1.
PIC18F87K22 FAMILY
12.1
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than V
All of the digital ports are 5.5V input tolerant. The ana-
log ports have the same tolerance – having clamping
diodes implemented internally.
12.1.1
When used as digital I/O, the output pin drive strengths
vary, according to the pins’ grouping, to meet the needs
for a variety of applications. In general, there are two
classes of output pins, in terms of drive capability:
• Outputs designed to drive higher current loads,
• Outputs with lower drive levels, but capable of
12.1.2
Four of the I/O ports (PORTB, PORTD, PORTE and
PORTJ) implement configurable weak pull-ups on all
pins. These are internal pull-ups that allow floating
digital input signals to be pulled to a consistent level
without the use of external resistors.
The pull-ups are enabled with a single bit for each of the
ports: RBPU (INTCON2<7>) for PORTB, and RDPU,
REPU and RJPU (PADCFG1<7:5>) for the other ports.
such as LEDs:
- PORTA
- PORTC
driving normal digital circuit loads with a high input
impedance. Able to drive LEDs, but only those
with smaller current requirements:
- PORTD
- PORTF
- PORTH
† These ports are not available on 64-pin
devices.
I/O Port Pin Capabilities
PIN OUTPUT DRIVE
PULL-UP CONFIGURATION
(†)
- PORTB
- PORTE
- PORTG
- PORTJ
(†)
DS39960D-page 165
DD
input levels.