PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 268

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
20.4.1
In Half-Bridge mode, two pins are used as outputs to
drive push-pull loads. The PWM output signal is output
on the PxA pin, while the complementary PWM output
signal is output on the PxB pin (see
mode can be used for half-bridge applications, as
shown in
where four power switches are being modulated with
two PWM signals.
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in
half-bridge power devices. The value of the PxDC<6:0>
bits of the ECCPxDEL register sets the number of
instruction cycles before the output is driven active. If the
value is greater than the duty cycle, the corresponding
output remains inactive during the entire cycle. For more
details on the dead-band delay operations, see
Section 20.4.6 “Programmable Dead-Band Delay
Mode”.
FIGURE 20-7:
DS39960D-page 268
Figure
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
HALF-BRIDGE MODE
20-7, or for full-bridge applications,
EXAMPLE OF HALF-BRIDGE APPLICATIONS
PxA
PxB
Figure
20-6). This
PxA
PxB
FET
Driver
FET
Driver
FET
Driver
FET
Driver
Since the PxA and PxB outputs are multiplexed with the
port data latches, the associated TRIS bits must be
cleared to configure PxA and PxB as outputs.
FIGURE 20-6:
PxA
PxB
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
(2)
(2)
2: Output signals are shown as active-high.
(1)
Load
V+
Pulse Width
td
PR2 register.
Period
 2009-2011 Microchip Technology Inc.
Load
td
EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
FET
Driver
FET
Driver
(1)
+
-
+
-
Period
(1)