PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 89

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.1.2
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and contained in three separate 8-bit registers.
The low byte, known as the PCL register, is both
readable and writable. The high byte, or PCH register,
contains the PC<15:8> bits and is not directly readable
or writable. Updates to the PCH register are performed
through the PCLATH register. The upper byte is called
PCU. This register contains the PC<20:16> bits; it is
also not directly readable or writable. Updates to the
PCU register are performed through the PCLATU
register.
The contents of PCLATH and PCLATU are transferred
to the Program Counter by any operation that writes
PCL. Similarly, the upper two bytes of the Program
Counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see
GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by two to address
sequential instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the Program Counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the Program Counter.
6.1.3
The return address stack enables execution of any
combination of up to 31 program calls and interrupts.
The PC is pushed onto the stack when a CALL or
RCALL instruction is executed or an interrupt is
Acknowledged. The PC value is pulled off the stack on
a RETURN, RETLW or a RETFIE instruction. The value
also is pulled off the stack on ADDULNK and SUBULNK
instructions, if the extended instruction set is enabled.
PCLATU and PCLATH are not affected by any of the
RETURN or CALL instructions.
FIGURE 6-3:
 2009-2011 Microchip Technology Inc.
PROGRAM COUNTER
RETURN ADDRESS STACK
Top-of-Stack Registers
TOSU
00h
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Section 6.1.5.1 “Computed
TOSH
1Ah
TOSL
34h
Top-of-Stack
Return Address Stack <20:0>
001A34h
000D58h
PIC18F87K22 FAMILY
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the
Top-of-Stack Special Function Registers. Data can also
be pushed to, or popped from, the stack using these
registers.
A CALL type instruction causes a push onto the stack.
The Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
a pop from the stack. The contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full, has overflowed or has underflowed.
6.1.3.1
Only the top of the return address stack (TOS) is
readable and writable. A set of three registers,
TOSU:TOSH:TOSL, holds the contents of the stack
location
(Figure
stack, if necessary. After a CALL, RCALL or interrupt (or
ADDULNK and SUBULNK instructions, if the extended
instruction set is enabled), the software can read the
pushed value by reading the TOSU:TOSH:TOSL regis-
ters. These values can be placed on a user-defined
software stack. At return time, the software can return
these values to TOSU:TOSH:TOSL and do a return.
While accessing the stack, users must disable the
Global Interrupt Enable bits to prevent inadvertent
stack corruption.
11111
11110
11101
00011
00010
00001
00000
6-3). This allows users to implement a software
pointed
Top-of-Stack Access
to
by
STKPTR<4:0>
Stack Pointer
00010
the
STKPTR
DS39960D-page 89
register