PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 99

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 6-2:
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FE6h
FE5h
FE4h
FE3h
FE2h
FE1h
FE0h
FDFh
FDEh
FDDh
FDCh
FDBh
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
FBFh
FBEh
FBDh
FBCh
FBBh
FBAh
FB9h
FB8h
FB7h
Note 1:
Address
2:
3:
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
FSR1L
BSR
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
SPBRGH1
OSCCON
IPR5
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSP1BUF
SSP1ADD
SSP1STAT
SSP1CON1
SSP1CON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
ECCP1AS
ECCP1DEL
CCPR1H
CCPR1L
CCP1CON
PIR5
PIE5
IPR4
PIR4
This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
File Name
PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value of
FSR1 offset by W
Indirect Data Memory Address Pointer 1 Low Byte
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value of
FSR2 offset by W
Indirect Data Memory Address Pointer 2 Low Byte
Timer0 Register High Byte
Timer0 Register Low Byte
USART1 Baud Rate Generator High Byte
Timer1 Register High Byte
Timer1 Register Low Byte
Timer2 Register
Timer2 Period Register
MSSP Receive Buffer/Transmit Register
MSSP Address Register in I
A/D Result Register High Byte
A/D Result Register Low Byte
Capture/Compare/PWM Register1 High Byte
Capture/Compare/PWM Register1 Low Byte
TMR7GIP
ECCP1ASE
TMR7GIF
TMR7GIE
CCP10IP
CCP10IF
TRIGSEL1
TMR1CS1
TMR0ON
REGSLP
P1RSEN
WCOL
IDLEN
GCEN
ADFM
P1M1
IPEN
Bit 7
SMP
—
—
—
—
—
—
(3)
(3)
(3)
(3)
(3)
TMR12IP
ECCP1AS2 ECCP1AS1
TMR12IE
T2OUTPS3 T2OUTPS2
TMR12IF
TRIGSEL0
TMR1CS0
ACKSTAT
CCP9IP
CCP9IF
SBOREN
SSPOV
T08BIT
P1DC6
IRCF2
CHS4
P1M0
Bit 6
CKE
—
—
—
—
—
—
(3)
(3)
(3)
(3)
(3)
2
C™ Slave Mode. SSP1 Baud Rate Reload Register in I
TMR10IP
TMR10IF
TMR10IE
T1CKPS1
ULPLVL
CCP8IP
CCP8IF
SSPEN
ACKDT
VCFG1
ACQT2
P1DC5
DC1B1
IRCF1
CHS3
T0CS
Bit 5
CM
D/A
—
—
—
—
(3)
(3)
(3)
T2OUTPS1
ECCP1AS0
T1CKPS0
SRETEN
TMR8IP
TMR8IF
TMR8IE
CCP7IP
CCP7IF
ACKEN
VCFG0
ACQT1
P1DC4
DC1B0
IRCF0
CHS2
T0SE
Bit 4
CKP
—
—
—
RI
N
P
PIC18F87K22 FAMILY
Indirect Data Memory Address Pointer 1 High
Bank Select Register
Indirect Data Memory Address Pointer 2 High
T2OUTPS0
TMR7IP
TMR7IF
TMR7IE
PSS1AC1
SOSCEN
CCP1M3
VNCFG
CCP6IP
CCP6IF
SSPM3
ACQT0
P1DC3
RCEN
OSTS
CHS1
Bit 3
PSA
OV
TO
—
S
(3)
(3)
(3)
PSS1AC0
TMR2ON
CCP1M2
T1SYNC
HFIOFS
TMR6IP
TMR6IE
TMR6IF
CCP5IP
CCP5IF
ULPEN
SSPM2
CHSN2
ADCS2
TOPS2
P1DC2
CHS0
Bit 2
PEN
R/W
PD
Z
2
C Master Mode.
GO/DONE
T2CKPS1
PSS1BD1
ULPSINK
CCP1M1
TMR5IP
TMR5IF
TMR5IE
CCP4IP
CCP4IF
TOPS1
SSPM1
CHSN1
ADCS1
P1DC1
RSEN
SCS1
RD16
POR
Bit 1
DC
UA
T2CKPS0
PSS1BD0
SWDTEN
TMR1ON
CCP1M0
TMR4IP
TMR4IE
TMR4IF
CCP3IP
CCP3IF
SSPM0
CHSN0
ADCS0
TOPS0
P1DC0
ADON
DS39960D-page 99
SCS0
Bit 0
BOR
SEN
BF
C
1111 1111
---- ----
---- ----
---- ----
---- ----
---- xxxx
xxxx xxxx
---- 0000
---- ----
---- ----
---- ----
---- ----
---- ----
---- xxxx
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
0000 0000
0110 q000
0-x0 -000
0111 11qq
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
-000 0000
0000 0000
0-00 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
1111 1111
0000 0000
POR, BOR
Value on