PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 405

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PIC18F67K22-I/MR

Manufacturer Part Number
PIC18F67K22-I/MR
Description
128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet

Specifications of PIC18F67K22-I/MR

Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F67K22-I/MRRSL
Manufacturer:
FSC
Quantity:
250
REGISTER 28-1:
 2009-2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4-3
bit 2
bit 1
bit 0
U-0
Unimplemented: Read as ‘ 0 ’
XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode are enabled
0 = Instruction set extension and Indexed Addressing mode are disabled (Legacy mode)
Unimplemented: Read as ‘ 0 ’
SOSCSEL<1:0>: SOSC Power Selection and Mode Configuration bits
11 = High-power SOSC circuit is selected
10 = Digital (SCLKI) mode; I/O port functionality of RC0 and RC1 is enabled
01 = Low-power SOSC circuit is selected
00 = Reserved
INTOSCSEL: LF-INTOSC Low-power Enable bit
1 = LF-INTOSC is in High-Power mode during Sleep
0 = LF-INTOSC is in Low-Power mode during Sleep
Unimplemented: Read as ‘ 0 ’
RETEN: V
1 = Regulator power while in Sleep mode is controlled by VREGSLP (WDTCON<7>)
0 = Regulator power while in Sleep mode is controlled by SRETEN (WDTCON<4>). Ultra low-power
XINST
R/P-1
regulator is enabled.
CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
REG
P = Programmable bit
W = Writable bit
‘1’ = Bit is set
Sleep Enable bit
U-0
SOSCSEL1 SOSCSEL0
R/P-1
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F87K22 FAMILY
R/P-1
INTOSCSEL
R/P-1
x = Bit is unknown
U-0
DS39960D-page 405
RETEN
R/P-1
bit 0

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