PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 215

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.2
Timer3, Timer5 and Timer7 can operate in these
modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
• Timer with Gated Control
FIGURE 16-1:
 2009-2011 Microchip Technology Inc.
Note 1:
T1CON.SOSCEN
T3CON.SOSCEN
SCS<1:0> = 01
T3G
From TMR4
Match PR4
From Comparator 1
Output
From Comparator 2
Output
Timer3/5/7 Operation
2:
3:
4:
T3GSS<1:0>
SOSCGO
SOSCO/SCLKI
ST Buffer is high-speed type when using T3CKI.
Timer3 registers increment on rising edge.
Synchronization does not operate while in Sleep.
The output of SOSC is determined by the SOSCSEL<1:0> Configuration bits.
T3GPOL
SOSCI
T3CKI
Set Flag bit
TMR3IF on
Overflow
TIMER3/5/7 BLOCK DIAGRAM
00
10
11
01
TMR3ON
T3GTM
TMR3H
EN
OUT
SOSC
TMR3
(1)
T3G_IN
(4)
(2)
D
R
CK
TMR3L
Q
Q
1
0
TMR3CS<1:0>
0
1
T3GGO/T3DONE
Q
Internal
Internal
F
OSC
Clock
Clock
F
PIC18F87K22 FAMILY
OSC
EN
/4
D
The operating mode is determined by the clock select
bits, TMRxCSx (TxCON<7:6>). When the TMRxCSx bits
are cleared (= 00), Timer3/5/7 increments on every inter-
nal instruction cycle (F
Timer3/5/7 clock source is the system clock (F
when it is ‘10’, Timer3/5/7 works as a counter from the
external clock from the TxCKI pin (on the rising edge after
the first falling edge) or the SOSC oscillator.
Single Pulse
Acq. Control
10
01
00
T3CLK
T3GSPM
T3CKPS<1:0>
T3SYNC
Prescaler
1, 2, 4, 8
TMR3ON
0
1
2
0
1
Internal
F
OSC
Clock
T3GVAL
OSC
TMR3GE
/2
/4). When TMRxCSx = 01, the
Q1
Synchronized
Synchronize
Interrupt
Clock Input
D
EN
Sleep Input
det
det
Q
DS39960D-page 215
(3)
Set
TMR3GIF
Data Bus
RD
T3GCON
OSC
), and