PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 73

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.0
The PIC18F87K22 family of devices differentiates
between various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
i)
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 6.1.3.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in
Timer
A simplified block diagram of the on-chip Reset circuit
is shown in
FIGURE 5-1:
 2009-2011 Microchip Technology Inc.
MCLR
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog Timer (WDT) Reset (during
execution)
Configuration Mismatch (CM) Reset
Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
V
(WDT)”.
DD
RESET
Figure
Configuration Word Mismatch
PWRT
Pointer
Stack
LF-INTOSC
( )_IDLE
V
Brown-out
32 s
Time-out
5-1.
DD
Detect
WDT
Reset
Sleep
Rise
External Reset
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Stack Full/Underflow Reset
RESET Instruction
POR Pulse
PWRT
Section 28.2 “Watchdog
11-Bit Ripple Counter
66 ms
PIC18F87K22 FAMILY
5.1
Device Reset events are tracked through the RCON
register
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event.
The state of these flag bits, taken together, can be read
to indicate the type of Reset that just occurred. This is
described in more detail in
of
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in
Section 11.0
Registers”.
RCON Register
(Register
“Interrupts”.
5-1). The lower five bits of the
S
R
Section 5.7 “Reset State
Q
DS39960D-page 73
Chip_Reset