PIC18F67K22-I/MR Microchip Technology, PIC18F67K22-I/MR Datasheet - Page 179

• Manufacturer Part Number: PIC18F67K22-I/MR
• Description: 128kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K22-I/MR

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 12-9:
 2009-2011 Microchip Technology Inc.
RE2/CS/P2B/
CCP10/AD10
RE3/P3C/
CCP9/REFO/
AD11
RE4/P3B/
CCP8/AD12
RE5/P1C/
CCP7/AD13
RE6/P1B/
CCP6/AD14
Legend:
Note 1:
Pin Name
2:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared and in Microcontroller mode.
This feature is only available on PIC18F8XKXX devices.
Function
PORTE FUNCTIONS (CONTINUED)
CCP10
AD10
AD11
AD12
AD13
AD14
REFO
CCP9
CCP8
CCP7
CCP6
RE2
RE3
P3C
RE4
RE5
P1C
RE6
P2B
P3B
P1B
CS
(2)
(2)
(2)
(2)
(2)
Setting
TRIS
0
1
x
0
1
x
x
0
1
0
0
1
x
x
x
0
1
0
0
1
x
x
0
1
0
0
1
x
x
0
1
0
0
1
x
x
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
DIG
TTL
DIG
TTL
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
—
—
—
—
LATE<2> data output.
PORTE<2> data input.
Parallel Slave Port chip select.
ECCP2 PWM Output B.
May be configured for tri-state during Enhanced PWM shutdown events.
Capture 10 input/Compare 10 output/PWM10 output.
External memory interface, Address/Data Bit 10 output.
External memory interface, Data Bit 10 input.
LATE<3> data output.
PORTE<3> data input.
ECCP3 PWM Output C.
May be configured for tri-state during Enhanced PWM shutdown events.
CCP9 Compare/PWM output; takes priority over port data.
CCP9 capture input.
Reference output clock.
External memory interface, Address/Data Bit 11 output.
External memory interface, Data Bit 11 input.
LATE<4> data output.
PORTE<4> data input.
ECCP3 PWM Output B.
May be configured for tri-state during Enhanced PWM shutdown events.
CCP8 compare/PWM output; takes priority over port data.
CCP8 capture input.
External memory interface, Address/Data Bit 12 output.
External memory interface, Data Bit 12 input.
LATE<5> data output.
PORTE<5> data input.
ECCP1 PWM Output C.
May be configured for tri-state during Enhanced PWM shutdown events.
CCP7 compare/PWM output; takes priority over port data.
CCP7 capture input.
External memory interface, Address/Data Bit 13 output.
External memory interface, Data Bit 13 input.
LATE<6> data output.
PORTE<6> data input.
ECCP1 PWM Output B.
May be configured for tri-state during Enhanced PWM shutdown events.
CCP6 compare/PWM output; takes priority over port data.
CCP9 capture input.
External memory interface, Address/Data Bit 14 output.
External memory interface, Data Bit 14 input.
PIC18F87K22 FAMILY
Description
DS39960D-page 179