MPC8360EVVALFHA Freescale Semiconductor, MPC8360EVVALFHA Datasheet - Page 19

• Manufacturer Part Number: MPC8360EVVALFHA
• Description: IC MPU POWERQUICC II PRO 740TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8360EVVALFHA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 667MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 740-TBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 667MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 740
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.3V
• Operating Supply Voltage (max): 1.35V
• Operating Supply Voltage (min): 1.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 740
• Package Type: TBGA
• For Use With: MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Table 12
5.3
This section specify the limits of the AC electrical characteristics for the operation of the QUICC Engine
block’s communication interfaces.
Table 13
core frequency for each interface.
Freescale Semiconductor
PLL lock times
DLL lock times
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
2. The csb_clk is determined by the CLKIN and system PLL ratio. See
Ethernet Management: MDC/MDIO
MII
RMII
GMII/RGMII/TBI/RTBI
SPI (master/slave)
UCC through TDM
MCC
UTOPIA L2
POS-PHY L2
HDLC bus
HDLC/transparent
results in the minimum and an 8:1 ratio results in the maximum.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
provides the PLL and DLL lock times.
lists the maximal QUICC Engine block I/O frequencies and the minimal QUICC Engine block
QUICC Engine Block Operating Frequency Limitations
The settings listed below are required for correct hardware interface
operation. Each protocol by itself requires a minimal QUICC Engine block
operating frequency setting for meeting the performance target. Because the
performance is a complex function of all the QUICC Engine block settings,
the user should make use of the QUICC Engine block performance utility
tool provided by Freescale to validate their system.
Interface
Parameter/Condition
Table 13. QUICC Engine Block Operating Frequency Limitations
Table 12. PLL and DLL Lock Times
Interface Operating
Frequency (MHz)
10 (max)
125 (typ)
10 (max)
50 (max)
25 (max)
50 (max)
50 (max)
10 (max)
50 (max)
25 (typ)
50 (typ)
NOTE
7680
Min
—
Section 22, “Clocking,”
Max Interface Bit
Rate (Mbps)
16.67
1000
100
100
800
800
10
10
70
10
50
122,880
Max
100
Min QUICC Engine
for more information.
Frequency
Operating
csb_clk cycles
8/3 × F
16 × F
8 × F
2 × F
2 × F
250
20
50
50
20
20
Unit
μs
1
(MHz)
RESET Initialization
Notes
Notes
1, 2
2, 4
2, 3
—
—
—
—
—
—
—
2
2
2
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