MPC8360EVVALFHA Freescale Semiconductor, MPC8360EVVALFHA Datasheet - Page 5

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MPC8360EVVALFHA

Manufacturer Part Number
MPC8360EVVALFHA
Description
IC MPU POWERQUICC II PRO 740TBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC II PROr
Datasheet

Specifications of MPC8360EVVALFHA

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
667MHz
Voltage
1.3V
Mounting Type
Surface Mount
Package / Case
740-TBGA
Core Size
32 Bit
Program Memory Size
64KB
Cpu Speed
667MHz
Embedded Interface Type
I2C, SPI, USB, UART
Digital Ic Case Style
TBGA
No. Of Pins
740
Rohs Compliant
Yes
Family Name
MPC83xx
Device Core
PowerQUICC II Pro
Device Core Size
32b
Frequency (max)
667MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.3V
Operating Supply Voltage (max)
1.35V
Operating Supply Voltage (min)
1.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
740
Package Type
TBGA
For Use With
MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8360EVVALFHA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8360EVVALFHA
Manufacturer:
FREESCALE
Quantity:
20 000
Freescale Semiconductor
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
— One multichannel communication controller (MCC) only on the MPC8360E supporting the
— Two UTOPIA/POS interfaces on the MPC8360E supporting 124 MultiPHY each (optional
— Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management
— Eight TDM interfaces on the MPC8360E and four TDM interfaces on the MPC8358E with
— Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC
— Four independent 16-bit timers that can be interconnected as four 32-bit timers
— Interworking functionality:
Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
802.11i®, iSCSI, and IKE processing. The security engine contains four crypto-channels, a
controller, and a set of crypto execution units (EUs).
— Public key execution unit (PKEU) supporting the following:
— Data encryption standard execution unit (DEU)
— Advanced encryption standard unit (AESU)
– Asynchronous HDLC
– UART
– BISYNC up to 2 Mbps
– User-programmable Virtual FIFO size
– QUICC multichannel controller (QMC) for 64 TDM channels
following:
– 256 HDLC or transparent channels
– 128 SS7 channels
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
2*128 MultiPHY with extended address) and one UTOPIA/POS interface on the MPC8358E
supporting 31/124 MultiPHY
1-bit mode for E3/T3 rates in clear channel
and MCC serial channels (MCC is only available on the MPC8360E)
– Layer 2 10/100-Base T Ethernet switch
– ATM-to-ATM switching (AAL0, 2, 5)
– Ethernet-to-ATM switching with L3/L4 support
– PPP interworking
– RSA and Diffie-Hellman
– Programmable field size up to 2048 bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511 bits
– DES, 3DES
– Two key (K1, K2) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
interfaces
Overview
5

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