MPC8360EVVALFHA Freescale Semiconductor, MPC8360EVVALFHA Datasheet - Page 92

• Manufacturer Part Number: MPC8360EVVALFHA
• Description: IC MPU POWERQUICC II PRO 740TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8360EVVALFHA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 667MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 740-TBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 667MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 740
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.3V
• Operating Supply Voltage (max): 1.35V
• Operating Supply Voltage (min): 1.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 740
• Package Type: TBGA
• For Use With: MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Clocking
22.3
The QUICC Engine block PLL is controlled by the RCWL[CEPMF], RCWL[CEPDF], and
RCWL[CEVCOD] parameters.
block PLL.
92
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
QUICC Engine Block PLL Configuration
Core VCO frequency = Core frequency × VCO divider. The VCO divider
(RCWL[COREPLL[0:1]]) must be set properly so that the core VCO
frequency is in the range of 800–1800 MHz. Having a core frequency below
the CSB frequency is not a possible option because the core frequency must
be equal to or greater than the CSB frequency.
RCWL[CEPMF] RCWL[CEPDF]
0–1
11
00
01
10
11
00
01
10
11
00
01
10
11
Table 74. QUICC Engine Block PLL Multiplication Factors
00000
00001
00010
00011
00100
RCWL[COREPLL]
Table 73. e300 Core PLL Configuration (continued)
Table 74
0001
0010
0010
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
2–5
shows the multiplication factor encodings for the QUICC Engine
0
0
0
0
0
6
1
0
0
0
0
1
1
1
1
0
0
0
0
NOTE
Multiplication Factor = RCWL[CEPMF]/
core_clk : csb_clk
Ratio
1.5:1
2.5:1
2.5:1
2.5:1
2.5:1
2:1
2:1
2:1
2:1
3:1
3:1
3:1
3:1
(1 + RCWL[CEPDF])
QUICC Engine PLL
Reserved
× 16
× 2
× 3
× 4
VCO divider
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
8
2
4
8
8
2
4
8
8
2
4
8
8
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