MPC8360EVVALFHA Freescale Semiconductor, MPC8360EVVALFHA Datasheet - Page 94

• Manufacturer Part Number: MPC8360EVVALFHA
• Description: IC MPU POWERQUICC II PRO 740TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8360EVVALFHA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 667MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 740-TBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 667MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 740
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.3V
• Operating Supply Voltage (max): 1.35V
• Operating Supply Voltage (min): 1.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 740
• Package Type: TBGA
• For Use With: MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Clocking
The RCWL[CEVCOD] denotes the QUICC Engine Block PLL VCO internal frequency as shown in
Table
The QUICC Engine block VCO frequency is derived from the following equations:
94
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
75.
ce_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF)
QE VCO Frequency = ce_clk × VCO divider × (1 + CEPDF)
The VCO divider (RCWL[CEVCOD]) must be set properly so that the
QUICC Engine block VCO frequency is in the range of 600–1400 MHz.
The QUICC Engine block frequency is not restricted by the CSB and core
frequencies. The CSB, core, and QUICC Engine block frequencies should
be selected according to the performance requirements.
Table 74. QUICC Engine Block PLL Multiplication Factors (continued)
Note:
1. Reserved modes are not listed.
RCWL[CEPMF] RCWL[CEPDF]
01011
01101
01111
10001
10011
10101
10111
11001
11011
11101
Table 75. QUICC Engine Block PLL VCO Divider
RCWL[CEVCOD]
1
1
1
1
1
1
1
1
1
1
00
01
10
11
NOTE
Multiplication Factor = RCWL[CEPMF]/
VCO Divider
Reserved
(1 + RCWL[CEPDF])
QUICC Engine PLL
4
8
2
× 10.5
× 11.5
× 12.5
× 13.5
× 14.5
× 5.5
× 6.5
× 7.5
× 8.5
× 9.5
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