MPC8360EVVALFHA Freescale Semiconductor, MPC8360EVVALFHA Datasheet - Page 31

• Manufacturer Part Number: MPC8360EVVALFHA
• Description: IC MPU POWERQUICC II PRO 740TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8360EVVALFHA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 667MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 740-TBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 667MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 740
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.3V
• Operating Supply Voltage (max): 1.35V
• Operating Supply Voltage (min): 1.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 740
• Package Type: TBGA
• For Use With: MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Figure 11
8.2.2
This section describes the MII transmit and receive AC timing specifications.
8.2.2.1
Table 29
Freescale Semiconductor
At recommended operating conditions with LV
At recommended operating conditions with LV
RX_CLK clock fall time, (80% to 20%)
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. In rev. 2.0 silicon, due to errata, t
TX_CLK clock period 10 Mbps
TX_CLK clock period 100 Mbps
TX_CLK duty cycle
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
inputs and t
timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
going to the high state (H) or setup time. Also, t
input signals (D) went invalid (X) relative to the t
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of t
is used with the appropriate letter: R (rise) or F (fall).
QE_ENET18 in Chip Errata for the MPC8360E, Rev. 1 .
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
provides the MII transmit AC timing specifications.
shows the GMII receive AC timing diagram.
MII AC Timing Specifications
(first two letters of functional block)(reference)(state)(signal)(state)
MII Transmit AC Timing Specifications
RXD[7:0]
Parameter/Condition
RX_CLK
RX_DV
RX_ER
Parameter/Condition
Table 28. GMII Receive AC Timing Specifications (continued)
GRX
Table 29. MII Transmit AC Timing Specifications
GRDXKH
Figure 11. GMII Receive AC Timing Diagram
represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention
t
t
GRXH
GRDVKH
DD
DD
/OV
/OV
minimum is 0.5 which is not compliant with the standard. Refer to Errata
DD
t
DD
GRX
of 3.3 V ± 10%.
of 3.3 V ± 10%.
GRDXKL
GRX
clock reference (K) going to the low (L) state or hold time. Note that, in
symbolizes GMII receive timing (GR) with respect to the time data
Symbol
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
t
GRXF
t
GRXF
t
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
MTXH
Symbol
t
t
MTKHDX
MTKHDV
t
GRDXKH
t
t
MTX
MTX
1
/t
MTX
1
t
GRXR
Min
—
Min
35
—
—
—
1
Typ
—
GRDVKH
Typ
400
40
—
5
Max
symbolizes GMII receive
1.0
RX
clock reference (K)
Max
65
15
—
—
—
Unit
ns
Notes
Unit
for
—
ns
ns
ns
%
31