MPC8360EVVALFHA Freescale Semiconductor, MPC8360EVVALFHA Datasheet - Page 95

• Manufacturer Part Number: MPC8360EVVALFHA
• Description: IC MPU POWERQUICC II PRO 740TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8360EVVALFHA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 667MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 740-TBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 667MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 740
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.3V
• Operating Supply Voltage (max): 1.35V
• Operating Supply Voltage (min): 1.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 740
• Package Type: TBGA
• For Use With: MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

22.4
To simplify the PLL configurations, the device might be separated into two clock domains. The first
domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and
has the csb_clk as its input clock. The second clock domain has the QUICC Engine block PLL. The clock
domains are independent, and each of their PLLs are configured separately. Both of the domains has one
common input clock.
illustrates each of the clock domains separately. Any combination of clock domains setting with same
input clock are valid. Refer to
device.
Freescale Semiconductor
Conf
No.
s10
s11
s12
s13
s14
s15
s16
s17
s18
s1
s2
s3
s4
s5
s6
s7
s8
s9
c1
c2
c3
c4
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
1
SPMF
0100
0100
0101
0101
0110
0110
0111
0111
0111
1000
1000
1000
1001
1001
1001
1010
1010
1010
Suggested PLL Configurations
æ
æ
æ
æ
0000100
0000101
0000100
0000101
0000100
0000110
0000011
0000100
0000101
0000011
0000100
0000101
0000010
0000011
0000100
0000010
0000011
0000100
CORE
PLL
æ
æ
æ
æ
Table 76
CEPMF
01001
01100
01110
01111
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
Section 22, “Clocking,”
shows suggested PLL configurations for 33 and 66 MHz input clocks and
Table 76. Suggested PLL Configurations
CEPDF
33 MHz CLKIN/PCI_SYNC_IN Options
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
æ
0
0
0
0
Clock Freq
(MHz)
Input
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
CSB Freq
for the appropriate operating frequencies for your
(MHz)
133
133
166
166
200
200
233
233
233
266
266
266
300
300
300
333
333
333
—
—
—
—
Core Freq
(MHz)
266
333
333
416
400
600
350
466
583
400
533
667
300
450
600
333
500
667
—
—
—
—
Freq (MHz)
Engine
QUICC
300
400
466
500
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(MHz)
400
—
—
—
—
—
—
—
—
—
—
—
—
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
(MHz)
533
—
—
—
—
—
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
Clocking
(MHz)
667
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
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