PIC16F716-I/P Microchip Technology Inc., PIC16F716-I/P Datasheet - Page 23

• Manufacturer Part Number: PIC16F716-I/P
• Description: 18 PIN, 3.5 KB FLASH, 128 RAM, 13 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F716-I/P

• A/d Inputs: 4-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 13
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

3.2
PORTB is an 8-bit wide bidirectional port. The
corresponding data direction register is TRISB. Setting
a TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a High-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
EXAMPLE 3-2:
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (OPTION_REG<7>).
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
FIGURE 3-3:
 2003 Microchip Technology Inc.
BCF
CLRF
BSF
MOVLW
MOVWF
RBPU
DATA
BUS
WR
PORT
Note
WR
TRIS
ECCPAS2: ECCP Auto-shutdown input
RB0/INT
(1)
1:
PORTB and the TRISB Register
STATUS, RP0
PORTB
STATUS, RP0
0xCF
TRISB
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
RD TRIS
RD PORT
TRIS Latch
Data Latch
D
D
CK
CK
Q
Q
Schmitt Trigger
Buffer
BLOCK DIAGRAM OF
RB0/INT/ECCPAS2 PIN
INITIALIZING PORTB
Q
;select Bank 0
;Initialize PORTB by
;clearing output
;data latches
;Select Bank 1
;Value used to
;initialize data
;direction
;Set RB<3:0> as inputs
;RB<5:4> as outputs
;RB<7:6> as inputs
EN
D
TTL
Input
Buffer
V
P
DD
RD PORT
weak
pull-up
V
SS
V
DD
RB0/
INT/
ECCPAS2
Preliminary
PORTB pins RB7:RB0 are multiplexed with several
peripheral functions (Table 3-3).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTB pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (such as BSF, BCF, XORWF) with
TRISB as the destination should be avoided. The user
should refer to the corresponding peripheral section for
the correct TRIS bit settings.
Four of PORTB’s pins, RB7:RB4, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins, RB7:RB4, are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from Sleep. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
1.
2.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Perform a read of PORTB to end the mismatch
condition.
Clear flag bit RBIF.
PIC16F716
DS41206A-page 21