PIC16F716-I/P Microchip Technology Inc., PIC16F716-I/P Datasheet - Page 40

• Manufacturer Part Number: PIC16F716-I/P
• Description: 18 PIN, 3.5 KB FLASH, 128 RAM, 13 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F716-I/P

• A/d Inputs: 4-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 13
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F716
7.4
The Enhanced PWM mode provides additional PWM
output options for a broader range of control
applications. The module is an upwardly compatible
version of the standard CCP module and offers up to
four outputs, designated P1A through P1D. Users are
also able to select the polarity of the signal (either
active-high or active-low). The module’s Output mode
and polarity are configured by setting the P1M1:P1M0
and CCP1M3:CCP1M0 bits of the CCP1CON register
(CCP1CON<7:6> and CCP1CON<3:0>, respectively).
Figure 7-5 shows a simplified block diagram of PWM
operation. All control registers are double buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to
prevent glitches on any of the outputs. The exception is
the PWM Dead-band Delay, which is loaded at either
the duty cycle boundary or the boundary period
(whichever comes first). Because of the buffering, the
module waits until the assigned timer resets, instead of
starting immediately. This means that enhanced PWM
waveforms do not exactly match the standard PWM
waveforms, but are instead offset by one full instruction
cycle (4 T
As before, the user must manually configure the
appropriate TRISB bits for output.
FIGURE 7-5:
DS41206A-page 38
Note
CCPR1H (Slave)
Duty Cycle Registers
Comparator
ENHANCED PWM MODE
CCPR1L
OSC
PR2
TMR2
1:
Comparator
).
The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit
time base.
(Note 1)
Clear Timer,
set CCP1 pin and
latch D.C.
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
CCP1CON<5:4>
R
S
P1M<1:0>
Q
Preliminary
PWM1CON
Controller
Output
2
CCP1/P1A
P1C
P1D
P1B
7.4.1
The P1M1:P1M0 bits in the CCP1CON register allows
one of four configurations:
• Single Output
• Half-Bridge Output
• Full-Bridge Output Forward mode
• Full-Bridge Output Reverse mode
The Single Output mode is the Standard PWM mode
discussed in Section 7.3 “PWM Mode”. The Half-
Bridge and Full-Bridge Output modes are covered in
detail in the sections that follow.
The general relationship of the outputs in all
configurations is summarized in Figure 7-6.
4
CCP1M<3:0>
TRISB<3>
TRISB<5>
TRISB<6>
TRISB<7>
PWM OUTPUT CONFIGURATIONS
 2003 Microchip Technology Inc.
RB3/CCP1/P1A
RB5/P1B
RB6/P1C
RB7/P1D