PIC16F716-I/P Microchip Technology Inc., PIC16F716-I/P Datasheet - Page 44

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PIC16F716-I/P

Manufacturer Part Number
PIC16F716-I/P
Description
18 PIN, 3.5 KB FLASH, 128 RAM, 13 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC16F716-I/P

A/d Inputs
4-Channel, 8-Bit
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Input Output
13
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin PDIP
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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PIC16F716
7.4.2
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output
signal is output on the RB3/CCP1/P1A pin, while the
complementary PWM output signal is output on the
RB5/P1B pin (Figure 7-12). This mode can be used for
half-bridge applications, as shown in Figure 7-11 or for
full-bridge applications, where four power switches are
being modulated with two PWM signals.
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of
PWM1CON bits PDC6:PDC0 sets the number of
instruction cycles before the output is driven active. If
the value is greater than the duty cycle, the
corresponding output remains inactive during the entire
cycle. See Section 7.4.4 “Programmable Dead-
Band Delay” for more details of the dead-band delay
operations.
FIGURE 7-11:
DS41206A-page 42
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
HALF-BRIDGE MODE
PIC16F716
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
P1A
P1B
PIC16F716
P1A
P1B
FET
Driver
FET
Driver
Preliminary
FET
Driver
FET
Driver
Since the P1A and P1B outputs are multiplexed with
the PORTB<3> and PORTB<5> data latches, the
TRISB<3> and TRISB<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 7-10:
Note 1:
P1A
P1B
td = Dead-band Delay
Load
V+
V-
(2)
(2)
V+
V-
2:
(1)
At this time, the TMR2 register is equal to the
PR2 register.
Output signals are shown as active-high.
td
Duty Cycle
Load
Period
td
FET
Driver
FET
Driver
HALF-BRIDGE PWM
OUTPUT
 2003 Microchip Technology Inc.
+
V
-
+
V
-
(1)
Period
(1)

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