PIC16F716-I/P Microchip Technology Inc., PIC16F716-I/P Datasheet - Page 69

• Manufacturer Part Number: PIC16F716-I/P
• Description: 18 PIN, 3.5 KB FLASH, 128 RAM, 13 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F716-I/P

• A/d Inputs: 4-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 13
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

9.10.1
External interrupt on RB0/INT pin is edge triggered,
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling if the INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service
routine before re-enabling this interrupt. The INT
interrupt can wake-up the processor from Sleep, if bit
INTE was set prior to going into Sleep. The status of
global interrupt enable bit GIE decides whether or not
the processor branches to the interrupt vector following
wake-up. See Section 9.13 “Power-down Mode
(Sleep)” for details on Sleep mode.
9.10.2
An overflow (FFh
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 4.0 “Timer0 Module”).
9.10.3
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 3.2 “PORTB and the TRISB Register”).
EXAMPLE 9-1:
 2003 Microchip Technology Inc.
MOVWF
SWAPF
MOVWF
MOVF
MOVWF
CLRF
BCF
MOVF
MOVWF
:
:(ISR)
:
MOVF
MOVWF
MOVF
MOVWF
SWAPF
MOVWF
SWAPF
SWAPF
RETFIE
on
INT INTERRUPT
TMR0 INTERRUPT
PORTB INTCON CHANGE
the
W_TEMP
STATUS,W
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
STATUS, IRP
FSR, W
FSR_TEMP
FSR_TEMP,W
FSR
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
00h) in the TMR0 register will set
RB0/INT
SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
pin,
flag
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
;Return to Bank 0
;Copy FSR to W
;Copy FSR from W to FSR_TEMP
;Restore FSR
;Move W into FSR
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
;Return from interrupt and enable GIE
bit
INTF
Preliminary
9.11
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt, (i.e., W register and Status
register). This will have to be implemented in firmware.
Example 9-1 stores and restores the W, Status,
PCLATH and FSR registers. Context storage registers,
W_TEMP,
FSR_TEMP, must be defined in Common RAM which
are those addresses between 70h-7Fh in Bank 0 and
between F0h-FFh in Bank 1.
The example:
a)
b)
c)
d)
e)
f)
Stores the W register.
Stores the Status register in Bank 0.
Stores the PCLATH register
Stores the FSR register.
Executes the interrupt service routine code
(User-generated).
Restores all saved registers in reverse order
from which they were stored
Context Saving During Interrupts
STATUS_TEMP,
PIC16F716
PCLATH_TEMP
DS41206A-page 67
and