PIC16F716-I/P Microchip Technology Inc., PIC16F716-I/P Datasheet - Page 30

• Manufacturer Part Number: PIC16F716-I/P
• Description: 18 PIN, 3.5 KB FLASH, 128 RAM, 13 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F716-I/P

• A/d Inputs: 4-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 13
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F716
4.2.1
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution).
FIGURE 4-2:
TABLE 4-1:
DS41206A-page 28
01h
0Bh,8Bh
81h
85h
Legend:
Note 1:
Address
Note:
RA4/T0CKI
CLKOUT (=F
WDT Enable bit
Note:
Watchdog
pin
Timer
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0
Reserved bits, do not use.
SWITCHING PRESCALER
ASSIGNMENT
To avoid an unintended device Reset, a
specific instruction sequence (shown in
the PICmicro
Manual, DS33023) must be executed
when changing the prescaler assignment
from Timer0 to the WDT. This sequence
must be followed even if the WDT is
disabled.
TMR0
INTCON
OPTION_REG
TRISA
T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
OSC
Name
REGISTERS ASSOCIATED WITH TIMER0
/4)
T0SE
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
®
0
1
Timer0 module’s register
RBPU INTEDG T0CS
Bit 7
GIE
PSA
Mid-Range Reference
—
M
U
X
0
1
PEIE
Bit 6
T0CS
—
M
U
X
Bit 5
T0IE
—
0
8-bit Prescaler
8 - to - 1MUX
(1)
Time-out
8
M U X
WDT
Preliminary
T0SE
Bit 4
INTE
Bit 4
1
0
1
PSA
PORTA Data Direction Register
M
U
X
RBIE
Bit 3
PSA
4.3
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h. This overflow sets
bit T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt
service routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
Sleep since the timer is shut off during Sleep.
PSA
Bit 2
T0IF
PS2
PS2:PS0
Timer0 Interrupt
Cycles
SYNC
2
Bit 1
INTF
PS1
RBIF
Bit 0
PS0
 2003 Microchip Technology Inc.
TMR0 reg
Data Bus
xxxx xxxx
0000 000x
1111 1111
--11 1111
Value on:
POR,
BOR
8
Set flag bit T0IF
on Overflow
other Resets
Value on all
uuuu uuuu
0000 000u
1111 1111
--11 1111
.