PIC16F716-I/P Microchip Technology Inc., PIC16F716-I/P Datasheet - Page 37

• Manufacturer Part Number: PIC16F716-I/P
• Description: 18 PIN, 3.5 KB FLASH, 128 RAM, 13 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F716-I/P

• A/d Inputs: 4-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 13
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

7.2.1
The user must configure the RB3/CCP1/P1A pin as the
CCP1 output by clearing the TRISB<3> bit.
7.2.2
Timer1
Synchronized Counter mode if the ECCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
7.2.3
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. Only a CCP interrupt is
generated (if enabled).
7.2.4
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of the ECCP resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special event trigger output of the ECCP also starts
an A/D conversion (if the A/D module is enabled).
TABLE 7-2:
 2003 Microchip Technology Inc.
0Bh,8Bh
0Ch
0Eh
0Fh
10h
15h
16h
17h
86h
8Ch
Legend:
Address
Note:
must
INTCON
PIR1
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
TRISB
PIE1
CCP1 PIN CONFIGURATION
Clearing the CCP1CON register will force
the RB3/CCP1/P1A compare output latch
to the default low level. This is not the
PORTB I/O data latch.
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1.
Name
be
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
running
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1register
Capture/Compare/PWM register1 (LSB)
Capture/Compare/PWM register1 (MSB)
PORTB Data direction register
P1M1
Bit 7
GIE
—
—
—
P1M0
PEIE
ADIF
ADIE
Bit 6
in
—
Timer
T1CKPS1
DC1B1
Bit 5
T0IE
—
—
mode
T1CKPS0
DC1B0
INTE
Bit 4
—
—
Preliminary
or
T1OSCEN
CCP1M3
RBIE
Bit 3
—
—
FIGURE 7-2:
Note
RB3/CCP1/P1A
Pin
Note:
T1SYNC
CCP1M2
CCP1IE
CCP1IF
Bit 2
T0IF
Output Enable
TRISB<3>
1:
Special event trigger will reset Timer1, but not set
interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/
DONE (ADCON0<2>) which starts an A/D
conversion.
The special event trigger from the ECCP
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
TMR1CS
CCP1M1
TMR2IE
TMR2IF
Bit 1
INTF
Q
Special Event Trigger
R
S
CCP1CON<3:0>
Mode Select
TMR1ON
Output
CCP1M0
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Logic
TMR1IF
TMR1IE
Bit 0
RBIF
PIC16F716
(PIR1<2>)
Set flag bit CCP1IF
match
0000 000x
-0-- -000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
0000 0000
1111 1111
-0-- -000
Value on
POR,
BOR
DS41206A-page 35
CCPR1H CCPR1L
TMR1H
Comparator
0000 000u
-0-- -000
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
1111 1111
-0-- -000
Value on
all other
Resets
TMR1L