PIC16F716-I/P Microchip Technology Inc., PIC16F716-I/P Datasheet - Page 9

• Manufacturer Part Number: PIC16F716-I/P
• Description: 18 PIN, 3.5 KB FLASH, 128 RAM, 13 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F716-I/P

• A/d Inputs: 4-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 13
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

2.0
There are two memory blocks in the PIC16F716
PICmicro
(program memory and data memory) has its own bus
so that concurrent access can occur.
Additional information on device memory may be found
in the PICmicro
(DS33023).
2.1
The PIC16F716 has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. The
PIC16F716 has 2K x 14 words of program memory.
Accessing a location above the physically implemented
address will cause a wrap-around.
The Reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1:
 2003 Microchip Technology Inc.
CALL, RETURN
RETFIE, RETLW
MEMORY ORGANIZATION
Program Memory Organization
®
microcontroller
On-chip Program
Interrupt Vector
®
Stack Level 1
Stack Level 8
Reset Vector
Memory
Mid-Range Reference Manual,
PC<12:0>
PROGRAM MEMORY MAP
AND STACK OF
PIC16F716
13
device.
0000h
0004h
0005h
07FFh
0800h
1FFFh
Each
block
Preliminary
2.2
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
and RP0 of the Status register are the bank select bits.
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function
Registers
implemented as static RAM. All implemented banks
contain Special Function Registers. The upper 16
bytes of GPR space and some “high use” Special
Function Registers in Bank 0 are mirrored in Bank 1 for
code reduction and quicker access.
Note 1:
(status<6:5>)
2:
RP1:RP0
Data Memory Organization
Maintain Status bit 6 clear to ensure
upward compatibility with future products.
Not implemented
00
01
10
11
are
(1)
General
PIC16F716
Purpose
DS41206A-page 7
Bank
2
3
0
1
(2)
(2)
Registers,