PIC16F716-I/P Microchip Technology Inc., PIC16F716-I/P Datasheet - Page 32

• Manufacturer Part Number: PIC16F716-I/P
• Description: 18 PIN, 3.5 KB FLASH, 128 RAM, 13 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F716-I/P

• A/d Inputs: 4-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 13
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F716
FIGURE 5-1:
5.2
A crystal oscillator circuit is built in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The
oscillator is a low-power oscillator designed to operate
with a 32.768 kHz tuning fork crystal. It will continue to
run during Sleep.
The user must provide a software time delay to ensure
proper oscillator start-up.
5.3
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 interrupt, if enabled, is generated on overflow
TABLE 5-1:
DS41206A-page 30
0Bh,8Bh
0Ch
8Ch
0Eh
0Fh
10h
Legend:
Address
Note 1:
RB1/T1OSO/T1CKI
RB2/T1OSI
Note 1: Circuit guidelines for the LP oscillator
2: The Timer1 register pair, TMR1H and
Timer1 Oscillator
Timer1 Interrupt
INTCON
PIR1
PIE1
TMR1L
TMR1H
T1CON
Name
x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by the Timer1 module.
Set flag bit
TMR1IF on
Overflow
When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
(32 kHz), as shown in Section 9.2
“Oscillator Configurations”, also apply
to the Timer1 Oscillator.
TMR1L, in combination with the Timer1
overflow flag (TMR1IF) can be used as
the oscillator start-up stabilization timer.
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7 Bit 6
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
GIE
—
—
—
TIMER1 BLOCK DIAGRAM
ADIE
PEIE
ADIF
—
TMR1H
T1OSC
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Bit 5
T0IE
TMR1
—
—
TMR1L
Oscillator
Enable
T1OSCEN
INTE
Bit 4
—
—
(1)
Preliminary
Clock
F
Internal
OSC
RBIE
Bit 3
/4
TMR1ON
—
—
on/off
TMR1CS
1
0
which is latched in interrupt flag bit TMR1IF (PIR1<0>).
This interrupt can be enabled/disabled by setting/clear-
ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
5.4
If the ECCP module is configured in Compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
Timer1 must be configured for either Timer or
Synchronized Counter mode to take advantage of this
feature. If Timer1 is running in Asynchronous Counter
mode, this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from the ECCP, the write will take
precedence.
In this mode of operation, the CCPR1H:CCPR1L
register pair effectively becomes the period register for
Timer1.
CCP1IE
CCP1IF
Note:
Bit 2
T0IF
T1CKPS1:T1CKPS0
T1SYNC
Prescaler
1, 2, 4, 8
Resetting Timer1 using an ECCP
Trigger Output
The special event triggers from the ECCP
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
TMR2IE
TMR2IF
0
1
Bit 1
INTF
2
TMR1IF
TMR1IE
RBIF
Bit 0
 2003 Microchip Technology Inc.
Synchronized
clock input
Synchronize
Sleep input
det
0000 000x 0000 000u
-0-- -000 -0-- -000
-0-- -000 -0-- -000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on
POR,
BOR
Value on
all other
Resets