PIC16F716-I/P Microchip Technology Inc., PIC16F716-I/P Datasheet - Page 70

• Manufacturer Part Number: PIC16F716-I/P
• Description: 18 PIN, 3.5 KB FLASH, 128 RAM, 13 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F716-I/P

• A/d Inputs: 4-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 13
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F716
9.12
The Watchdog Timer is a free running, on-chip, RC
oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the OSC1/CLKIN pin. That means that
the WDT will run, even if the clock on the OSC1/CLKIN
and OSC2/CLKOUT pins of the device have been
stopped, for example, by execution of a SLEEP instruc-
tion.
During normal operation, a WDT time-out generates a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the Status register
will be cleared upon a Watchdog Timer time-out.
FIGURE 9-14:
FIGURE 9-15:
DS41206A-page 68
2007h
81h
Legend:
Note 1:
Address
Note:
Watchdog Timer (WDT)
Shaded cells are not used by the Watchdog Timer.
See Register 9-1 for operation of these bits.
Config. bits
OPTION_REG
PSA and PS2:PS0 are bits in the OPTION_REG register.
Name
WATCHDOG TIMER BLOCK DIAGRAM
SUMMARY OF WATCHDOG TIMER REGISTERS
WDT Timer
Enable Bit
WDT
Bits 13:8
N/A
From TMR0 Clock Source (Figure 4-2)
(1)
BORV
RBPU
Bit 7
(1)
0
1
PSA
M
U
X
Preliminary
BOREN
INTEDG
Bit 6
(1)
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 9.1 “Configuration
Bits”).
WDT time-out period values may be found in the
Electrical Specifications section under T
ter #31). Values for the WDT prescaler (actually a
postscaler, but shared with the Timer0 prescaler) may
be assigned using the OPTION_REG register.
.
T0CS
Bit 5
0
—
Note:
Note:
Time-out
8 - to - 1 MUX
MUX
WDT
Postscaler
T0SE
Bit 4
—
1
The CLRWDT and SLEEP instructions clear
the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out
and generating a device Reset condition.
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
8
PWRTE
Bit 3
PSA
PSA
To TMR0 (Figure 4-2)
(1)
 2003 Microchip Technology Inc.
PS2:PS0
WDTE
Bit 2
PS2
FOSC1
Bit 1
PS1
WDT
(parame-
FOSC0
Bit 0
PS0