PIC16F716-I/P Microchip Technology Inc., PIC16F716-I/P Datasheet - Page 29

• Manufacturer Part Number: PIC16F716-I/P
• Description: 18 PIN, 3.5 KB FLASH, 128 RAM, 13 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F716-I/P

• A/d Inputs: 4-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 13
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.0
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• Internal or external clock select
• Edge select for external clock
• 8-bit software programmable prescaler
• Interrupt on overflow from FFh to 00h
Figure 4-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the
(DS33023).
4.1
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If the TMR0 register is written, the
increment is inhibited for the following two instruction
cycles. The user can work around this by writing an
adjusted value to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment on every rising or falling edge of pin RA4/
T0CKI. The incrementing edge is determined by the
Timer0
(OPTION_REG<4>). Clearing bit T0SE selects the
rising edge. Restrictions on the external clock input are
discussed below.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (T
incrementing of Timer0 after synchronization.
Additional information on external clock requirements
is available in the PICmicro
Manual, (DS33023).
FIGURE 4-1:
 2003 Microchip Technology Inc.
RA4/T0CKI
pin
Note
PICmicro
TIMER0 MODULE
Timer0 Operation
Source
1:
2:
OSC
T0SE
®
T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
). Also, there is a delay in the actual
F
(1)
Mid-Range
OSC
Edge
/4
TIMER0 BLOCK DIAGRAM
®
T0CS
Select
Mid-Range Reference
Reference
0
1
(1)
PS2, PS1, PS0
bit
Programmable
Prescaler
Manual,
T0SE
3
Preliminary
(2)
(1)
PSA
1
0
(1)
4.2
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer, respectively (Figure 4-2). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet.
The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Setting bit PSA will assign the prescaler to the
Watchdog Timer (WDT). When the prescaler is
assigned to the WDT, prescale values of 1:1, 1:2, ...,
1:128 are selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT.
PS
Note:
Note:
Note:
OUT
(2 cycle delay)
1,x....etc.) will clear the prescaler. When
Sync with
Prescaler
Internal
clock
There is only one prescaler available,
which is mutually exclusively shared
between the Timer0 module and Watch-
dog Timer. Thus, a prescaler assignment
for the Timer0 module means that there is
no prescaler for the Watchdog Timer and
vice-versa.
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
PS
OUT
PIC16F716
Data Bus
TMR0
8
DS41206A-page 27
Set interrupt
flag bit T0IF
on overflow