PIC16F716-I/P Microchip Technology Inc., PIC16F716-I/P Datasheet - Page 50

• Manufacturer Part Number: PIC16F716-I/P
• Description: 18 PIN, 3.5 KB FLASH, 128 RAM, 13 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F716-I/P

• A/d Inputs: 4-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 13
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F716
7.4.7
The following steps should be taken when configuring
the ECCP module for PWM operation:
1.
2.
3.
4.
5.
6.
7.
TABLE 7-5:
DS41206A-page 48
0Bh
0Ch
8Ch
11h
92h
12h
86h
16h
15h
17h
19h
18h
Legend:
Address
Configure the PWM pins P1A and P1B (and
P1C and P1D, if used) as inputs by setting the
corresponding TRISB bits.
Set the PWM period by loading the PR2 register.
Configure the ECCP module for the desired
PWM mode and configuration by loading the
CCP1CON register with the appropriate values:
• Select
• Select the polarities of the PWM output
Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
For Half-Bridge Output mode, set the dead-
band delay by loading PWM1CON<6:0> with
the appropriate value.
If auto-shutdown operation is required, load the
ECCPAS register.
• Select the auto-shutdown sources using the
• Select the shutdown states of the PWM output
• Set the ECCPASE bit (ECCPAS<7>).
If auto-restart operation is required, set the
PRSEN bit (PWM1CON<7>).
configurations
P1M1:P1M0 bits.
signals with the CCP1M3:CCP1M0 bits.
ECCPAS<2> AND ECCPAS<0> bits.
pins
PSSBD1:PSSBD0 bits.
INTCON
PIR1
PIE1
TMR2
PR2
TRISB
CCPR1H
CCPR1L
CCP1CON
ECCPAS
PWM1CON
T2CON
Name
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the ECCP module in enhanced PWM mode.
SETUP FOR PWM OPERATION
using
one
REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2
Timer2 Module Register
Timer2 Module Period Register
PORTB Data Direction Register
Enhanced Capture/Compare/PWM Register1 High Byte
Enhanced Capture/Compare/PWM Register1 Low Byte
ECCPASE
PRSEN
P1M1
Bit 7
GIE
—
—
—
of
and
PSSAC1:PSSAC0
the
direction
TOUTPS3
ECCPAS2
PDC6
P1M0
ADIF
ADIE
Bit 6
PEIE
available
TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
with
TMR0IE
DC1B1
PDC5
Bit 5
—
—
—
output
and
the
Preliminary
ECCPAS0
INT0IE
DC1B0
PDC4
Bit 4
—
—
CCP1M3
PSSAC1
PDC3
RBIE
Bit 3
8.
9.
See the previous section for additional details.
7.4.8
Both Power-on and subsequent Resets will force all
ports to Input mode and the ECCP registers to their
Reset states.
This forces the Enhanced CCP module to reset to a
state compatible with the standard ECCP module.
—
—
Configure and start TMR2:
• Clear the TMR2 interrupt flag bit by clearing
• Set the TMR2 prescale value by loading the
• Enable Timer2 by setting the TMR2ON bit
Enable PWM outputs after a new PWM cycle
has started:
• Wait until TMR2 overflows (TMR2IF bit is set).
• Enable the CCP1/P1A, P1B, P1C and/or P1D
• Clear the ECCPASE bit (ECCPAS<7>).
the TMR2IF bit (PIR1<1>).
T2CKPSx bits (T2CON<1:0>).
(T2CON<2>).
pin outputs by clearing the respective TRISB
bits.
CCP1M2
PSSAC0
TMR0IF
CCP1IE
CCP1IF
PDC2
Bit 2
EFFECTS OF A RESET
CCP1M1
PSSBD1
TMR2IF
TMR2IE
INT0IF
PDC1
Bit 1
 2003 Microchip Technology Inc.
CCP1M0 0000 0000 0000 0000
PSSBD0 00-0 0000 00-0 0000
TMR1IF -0-- -000 -0-- -000
TMR1IE -0-- --00 -0-- --00
PDC0
RBIF
Bit 0
0000 000x 0000 000u
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
POR, BOR
Value on
Value on
all other
Resets