PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 122

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F6525/6621/8525/8621
10.7
PORTG is a 6-bit wide port with 5 bidirectional pins
(RG0:RG4) and one optional input only pin (RG5). The
corresponding data direction register is TRISG. Setting
a TRISG bit (= 1) will make the corresponding PORTG
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISG bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATG) is also memory
mapped. Read-modify-write operations on the LATG
register, read and write the latched output value for
PORTG.
PORTG is multiplexed with both CCP/ECCP and
EUSART functions (Table 10-13). PORTG pins have
Schmitt Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write operations of the
TRIS register without concern due to peripheral
overrides.
FIGURE 10-16:
DS39612B-page 120
Note:
RD LATG
Data Bus
RD TRISG
Peripheral Output
Enable
PORTG/Peripheral Out Select
Peripheral Data Out
WR PORTG
WR TRISG
RD PORTG
Peripheral Data In
WR LATG
PORTG, TRISG and LATG
Registers
(2)
On a Power-on Reset, these pins are
configured as digital inputs.
or
TRIS Latch
Data Latch
PORTG BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
D
D
CK
CK
Q
Q
Q
Q
Override
TRIS
Logic
0
1
Q
EN
D
Schmitt
Trigger
V
N
P
V
DD
SS
programming voltage input during device programming.
The sixth pin of PORTG (MCLR/V
input pin. Its operation is controlled by the MCLRE
configuration
(CONFIG3H<7>).
(MCLRE = 1), the pin functions as the device Master
Clear input. When selected as a port pin (MCLRE = 0),
it functions as an input only pin; as such, it does not
have TRISG or LATG bits associated with it.
In either configuration, RG5 also functions as the
EXAMPLE 10-7:
CLRF
CLRF
MOVLW
MOVWF
Note 1: On a Power-on Reset, RG5 is enabled as
I/O pin
2: If the device Master Clear is disabled,
(1)
PORTG
LATG
0x04
TRISG
a digital input only if Master Clear
functionality is disabled (MCLRE = 0).
verify that either of the following is done to
ensure proper entry into ICSP mode:
a.) disable low-voltage programming
b.) make certain that RB5/KBI1/PGM is
Note 1: I/O pins have diode protection to V
RG0
RG1
RG2
RG3
RG4
Pin
bit
(CONFIG4L<2> = 0); or
held low during entry into ICSP.
2: Peripheral output enable is only active
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
in
and V
if peripheral select is active.
In
Override
INITIALIZING PORTG
 2005 Microchip Technology Inc.
Yes
Yes
Yes
Yes
Yes
Configuration
SS
TRIS OVERRIDE
its
.
default
USART1 Async Xmit,
USART1 Async Rcv,
PP
Sync Data Out
Sync Clock
Peripheral
ECCP3 I/O
CCP4 I/O
CCP5 I/O
/RG5) is a digital
Register
configuration
DD
3H