PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 138

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F6525/6621/8525/8621
12.1
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input or the
Timer1 oscillator, if enabled.
FIGURE 12-1:
FIGURE 12-2:
DS39612B-page 136
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
T1OSO/T13CKI
Timer1 Operation
T1OSO/T13CKI
TMR1IF
Overflow
Interrupt
Flag bit
Data Bus<7:0>
Write TMR1L
Read TMR1L
TMR1IF
Overflow
Interrupt
Flag Bit
T1OSI
T1OSI
TIMER1 BLOCK DIAGRAM
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
8
T1OSC
T1OSC
High Byte
TMR1H
TMR1H
8
Timer 1
8
TMR1
TMR1
Oscillator
Enable
T1OSCEN
T1OSCEN
Enable
Oscillator
TMR1L
TMR1L
8
CLR
(1)
(1)
CLR
Internal
Clock
F
OSC
Internal
Clock
F
/4
TMR1ON
ECCP Special Event Trigger
OSC
On/Off
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored and the pins are read as ‘0’.
Timer1 also has an internal “Reset input”. This Reset
can be generated by the ECCP1 or ECCP2 special
event trigger. This is discussed in detail in Section 12.4
“Resetting Timer1 Using an ECCP Special Trigger
Output”.
TMR1CS
/4
TMR1ON
ECCP Special Event Trigger
1
0
On/Off
TMR1CS
1
0
T1CKPS1:T1CKPS0
T1SYNC
T1CKPS1:T1CKPS0
Prescaler
1, 2, 4, 8
0
1
T1SYNC
Prescaler
1, 2, 4, 8
2
1
0
2
 2005 Microchip Technology Inc.
Synchronized
Clock Input
Synchronize
Sleep Input
Synchronized
Clock Input
Synchronize
Sleep Input
det
det