PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 357

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 27-24:
TABLE 27-26: A/D CONVERSION REQUIREMENTS
 2005 Microchip Technology Inc.
130
131
132
135
136
Note 1:
Param.
No.
Note 1: If the A/D clock source is selected as RC, a time of T
A/D DATA
SAMPLE
2:
3:
4:
5:
A/D CLK
ADRES
BSF ADCON0, GO
2: This is a minimal RC delay (typically 100 ns) which also disconnects the holding capacitor from the analog input.
T
T
T
T
T
Symbol
ADIF
AD
CNV
ACQ
SWC
AMP
GO
ADRES register may be read on the following T
See Section 20.0 “10-Bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when input
voltage has changed more than 1 LSb.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AV
50Ω.
On the next Q4 cycle of the device clock.
The time of the A/D clock period is dependent on the device frequency and the T
Q4
This allows the SLEEP instruction to be executed.
132
A/D Clock Period
Conversion Time (not including acquisition
time) (Note 1)
Acquisition Time (Note 3)
Switching Time from Convert → Sample
Amplifier Settling Time (Note 2)
A/D CONVERSION TIMING
(Note 2)
Characteristic
9
DD
to AV
8
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
SS
PIC18F6525/6621/8525/8621
OLD_DATA
, or AV
7
CY
SS
. . .
SAMPLING STOPPED
is added before the A/D clock starts.
to AV
CY
. . .
DD
131
130
cycle.
). The source impedance (R
Min
1.6
3.0
2.0
3.0
11
15
10
—
1
2
(Note 4)
20
20
Max
6.0
9.0
12
—
—
—
1
(5)
(5)
Units
T
µs
µs
µs
µs
µs
µs
µs
AD
0
T
T
A/D RC mode
A/D RC mode
-40°C ≤ Temp ≤ +125°C
0°C ≤ Temp ≤ +125°C
This may be used if the
“new” input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from the
last sampled voltage (as
stated on C
OSC
OSC
AD
S
) on the input channels is
clock divider.
NEW_DATA
DONE
based, V
based, V
Conditions
DS39612B-page 355
T
HOLD
CY
REF
REF
).
≥ 3.0V
full range