PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 159

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

17.0
The Enhanced CCP (ECCP) modules differ from the
standard CCP modules by the addition of Enhanced
PWM capabilities. These allow for 2 or 4 output
channels, user selectable polarity, dead-band control
and automatic shutdown and restart and are discussed
in detail in Section 17.4 “Enhanced PWM Mode”.
Except for the addition of the special event trigger,
REGISTER 17-1:
 2005 Microchip Technology Inc.
ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULE
bit 7-6
bit 5-4
bit 3-0
CCPxCON REGISTER (ECCP1, ECCP2 AND ECCP3 MODULES)
Legend:
R = Readable bit
-n = Value at POR
bit 7
PxM1:PxM0: Enhanced PWM Output Configuration bits
If CCPxM3:CCPxM2 = 00, 01, 10:
xx = PxA assigned as Capture/Compare input/output; PxB, PxC, PxD assigned as port pins
If CCPxM3:CCPxM2 = 11:
00 = Single output: PxA modulated; PxB, PxC, PxD assigned as port pins
01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned
11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are
found in CCPRxL.
CCPxM3:CCPxM0: Enhanced CCP Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match
0011 = Capture mode
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, initialize ECCP pin low, set output on compare match (set CCPxIF)
1001 = Compare mode, initialize ECCP pin high, clear output on compare match (set CCPxIF)
1010 = Compare mode, generate software interrupt only, ECCP pin reverts to I/O state
1011 = Compare mode, trigger special event (ECCP resets TMR1 or TMR3, sets CCxIF bit,
1100 = PWM mode; PxA, PxC active-high; PxB, PxD active-high
1101 = PWM mode; PxA, PxC active-high; PxB, PxD active-low
1110 = PWM mode; PxA, PxC active-low; PxB, PxD active-high
1111 = PWM mode; PxA, PxC active-low; PxB, PxD active-low
R/W-0
PxM1
Note 1: Implemented only for ECCP1 and ECCP2; same as ‘1010’ for ECCP3.
as port pins
ECCP2 trigger starts A/D conversion if A/D module is enabled)
R/W-0
PxM0
PIC18F6525/6621/8525/8621
DCxB1
R/W-0
W = Writable bit
‘1’ = Bit is set
DCxB0
R/W-0
Capture and Compare functions of the ECCP module
are the same as the standard CCP module.
The prototype control register for the Enhanced CCP
module is shown in Register 17-1. In addition to the
expanded range of modes available through the
CCPxCON register, the ECCP modules each have two
additional registers associated with Enhanced PWM
operation and auto-shutdown features. They are:
• ECCPxDEL (Dead-Band Delay)
• ECCPxAS (Auto-Shutdown Configuration)
CCPxM3
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
CCPxM2
R/W-0
(1)
x = Bit is unknown
CCPxM1
R/W-0
DS39612B-page 157
CCPxM0
R/W-0
bit 0