PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 242

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F6525/6621/8525/8621
20.4
The ADCON1, TRISA, TRISF and TRISH registers
control the operation of the A/D port pins. The port pins
needed as analog inputs must have their corresponding
TRIS bits set (input). If the TRIS bit is cleared (output),
the digital output level (V
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
FIGURE 20-3:
DS39612B-page 240
Note 1: When reading the port register, all pins
T
Set GO/DONE bit
CY
2: Analog levels on any pin defined as a
Configuring Analog Port Pins
Holding capacitor is disconnected from analog input (typically 100 ns)
- T
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as a digital input will convert as an
analog input. Analog levels on a digitally
configured input will not affect the
conversion accuracy.
digital input may cause the input buffer to
consume current out of the device’s
specification limits.
AD
Conversion starts
T
AD
b9
1 T
A/D CONVERSION T
OH
AD
b8
or V
2 T
OL
AD
b7
) will be converted.
3 T
AD
b6
Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared,
4 T
AD
b5
AD
5 T
CYCLES
ADIF bit is set, holding capacitor is connected to analog input.
AD
b4
6 T
AD
b3
7 T
20.5
Figure 20-3 shows the operation of the A/D converter
after the GODONE bit has been set. Clearing the GO/
DONE bit during a conversion will abort the current
conversion. The A/D Result register pair will NOT be
updated with the partially completed A/D conversion
sample. That is, the ADRESH:ADRESL registers will
continue to contain the value of the last completed
conversion
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2 T
acquisition is started. After this 2 T
on the selected channel is automatically started.
AD
b2
Note:
8
T
AD
b1
A/D Conversions
9 T
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
(or
AD
b0
10
AD
the
T
wait is required before the next
AD
b0
 2005 Microchip Technology Inc.
last
11
value
AD
written
wait, acquisition
to
the