PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 223

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

19.2
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTAx<4>). In this mode, the
EUSART uses standard non-return-to-zero (NRZ) for-
mat (one Start bit, eight or nine data bits and one Stop
bit). The most common data format is 8 bits. An on-chip
dedicated 8-bit/16-bit Baud Rate Generator can be
used to derive standard baud rate frequencies from the
oscillator.
The EUSART transmits and receives the LSb first. The
EUSART module’s transmitter and receiver are
functionally independent but use the same data format
and baud rate. The Baud Rate Generator produces a
clock, either x16 or x64 of the bit shift rate depending
on the BRGH and BRG16 bits (TXSTAx<2> and
BAUDCONx<3>). Parity is not supported by the
hardware but can be implemented in software and
stored as the 9th data bit.
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
• Auto-Wake-up on Sync Break Character
• 12-bit Break Character Transmit
• Auto-Baud Rate Detection
19.2.1
The EUSART transmitter block diagram is shown in
Figure 19-2. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREGx. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREGx register (if available).
FIGURE 19-2:
 2005 Microchip Technology Inc.
EUSART Asynchronous Mode
BRG16
EUSART ASYNCHRONOUS
TRANSMITTER
TXxIE
Interrupt
EUSART TRANSMIT BLOCK DIAGRAM
SPBRGHx
Baud Rate Generator
TXxIF
TXEN
Baud Rate CLK
SPBRGx
MSb
(8)
PIC18F6525/6621/8525/8621
TXREGx Register
TSR Register
TX9D
• • •
TX9
8
Data Bus
Once the TXREGx register transfers the data to the TSR
register (occurs in one T
empty and flag bit TXxIF is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXxIE.
Flag bit TXxIF will be set regardless of the state of
enable bit TXxIE and cannot be cleared in software. Flag
bit TXxIF is not cleared immediately upon loading the
Transmit Buffer register, TXREGx. TXxIF becomes valid
in the second instruction cycle following the load instruc-
tion. Polling TXxIF immediately following a load of
TXREGx will return invalid results.
While flag bit TXxIF indicates the status of the TXREGx
register, another bit, TRMT (TXSTAx<1>), shows the
status of the TSR register. Status bit TRMT is a read-only
bit which is set when the TSR register is empty. No inter-
rupt logic is tied to this bit so the user has to poll this bit
in order to determine if the TSR register is empty.
To set up an Asynchronous Transmission:
1.
2.
3.
4.
5.
6.
7.
If using interrupts, ensure that the GIE and PEIE bits in
the INTCON register (INTCON<7:6>) are set.
Note 1: The TSR register is not mapped in data
Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit TXxIE.
If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
Enable the transmission by setting bit TXEN
which will also set bit TXxIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREGx register (starts
transmission).
LSb
2: Flag bit TXxIF is set when enable bit
0
memory so it is not available to the user.
TXEN is set.
TRMT
and Control
Pin Buffer
SPEN
CY
), the TXREGx register is
DS39612B-page 221
TXx pin