PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 163

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 17-1:
17.4.2
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPRxL:CCPxCON<5:4>. The PWM duty cycle is
calculated by the equation:
EQUATION 17-2:
CCPR1L and CCP1CON<5:4> can be written to at any
time but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
TABLE 17-4:
 2005 Microchip Technology Inc.
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
PWM Frequency
Note 1: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit
PWM DUTY CYCLE
CCPR1H (Slave)
Duty Cycle Registers
Comparator
CCPR1L
PR2
TMR2
Comparator
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
time base.
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
T
OSC
(Note 1)
• (TMR2 Prescale Value)
Clear Timer,
set ECCP1 pin and
latch D.C.
CCP1CON<5:4>
2.44 kHz
FFh
16
10
R
S
PIC18F6525/6621/8525/8621
9.77 kHz
P1M1<1:0>
Q
FFh
10
4
ECCP1DEL
39.06 kHz
Controller
The CCPRxH register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM opera-
tion. When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the ECCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 17-3:
ECCP1/P1A
Output
2
Note:
FFh
10
1
PWM Resolution (max) =
P1C
P1D
P1B
4
CCP1M<3:0>
If the PWM duty cycle value is longer than
the PWM period, the ECCP1 pin will not
be cleared.
156.25 kHz
TRISx<x>
TRISx<x>
TRISx<x>
TRISx<x>
3Fh
1
8
312.50 kHz
1Fh
log
1
7
(
log(2)
DS39612B-page 161
F
F
ECCP1/P1A
P1B
P1C
P1D
PWM
OSC
)
416.67 kHz
bits
6.58
17h
1