PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 317

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PIC18F6621-I/PT

Manufacturer Part Number
PIC18F6621-I/PT
Description
64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F6621-I/PT

A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
54
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
64-pin TQFP
Programmable Memory
64K Bytes
Ram Size
3.8K Bytes
Speed
40 MHz
Timers
2-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F6621-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F6621-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC18F6621-I/PT
Quantity:
2 850
TSTFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2005 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If CNT
If CNT
No
No
No
Q1
Q1
Q1
PC
PC
=
=
=
=
register ‘f’
operation
operation
operation
Test f, Skip if 0
[ label ]
0 ≤ f ≤ 255
a ∈ [0,1]
skip if f = 0
None
If ‘f’ = 0, the next instruction, fetched
during the current instruction execution
is discarded and a NOP is executed,
making this a two-cycle instruction. If ‘a’
is ‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as per
the BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0110
No
No
No
Q2
Q2
Q2
Address (HERE)
0x00,
Address (ZERO)
0x00,
Address (NZERO)
by a 2-word instruction.
TSTFSZ f [,a]
TSTFSZ
:
:
011a
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
CNT, 1
ffff
operation
operation
operation
operation
PIC18F6525/6621/8525/8621
No
No
No
No
Q4
Q4
Q4
ffff
XORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
=
=
0xB5
0x1A
literal ‘k’
Exclusive OR Literal with W
[ label ] XORLW k
0 ≤ k ≤ 255
(W) .XOR. k → W
N, Z
The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
1
1
XORLW
Read
Q2
0000
0xAF
1010
Process
Data
Q3
DS39612B-page 315
kkkk
Write to
Q4
W
kkkk

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