PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 261

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

24.0
There are several features intended to maximize
system reliability, minimize cost through elimination of
external components, provide power-saving operating
modes and offer code protection. These are:
• Oscillator Selection
• Reset
• Interrupts
• Watchdog Timer (WDT)
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming
All PIC18F6525/6621/8525/8621 devices have a
Watchdog Timer which is permanently enabled via the
configuration bits, or software controlled. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in Reset until the crystal oscillator is stable.
The other is the Power-up Timer (PWRT) which
provides a fixed delay on power-up only, designed to
keep the part in Reset while the power supply
stabilizes. With these two timers on-chip, most
applications need no external Reset circuitry.
TABLE 24-1:
 2005 Microchip Technology Inc.
300001h
300002h
300003h
300004h
300005h
300006h
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
3FFFFEh DEVID1
3FFFFFh DEVID2
Legend:
Note 1:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
File Name
2:
3:
(1)
SPECIAL FEATURES OF THE CPU
CONFIG4L
CONFIG1H
CONFIG2L
CONFIG2H
CONFIG3L
CONFIG3H MCLRE
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
x = unknown, u = unchanged, – = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Unimplemented in PIC18F6525/6621 devices; maintain this bit set.
Unimplemented in PIC18FX525 devices; maintain this bit set.
See Register 24-13 for DEVID1 values.
CONFIGURATION BITS AND DEVICE IDS
DEBUG
DEV10
WRTD
DEV2
WAIT
Bit 7
CPD
—
—
—
—
—
—
—
EBTRB
WRTB
DEV1
DEV9
Bit 6
CPB
—
—
—
—
—
—
—
—
—
OSCSEN
WRTC
DEV0
DEV8
Bit 5
PIC18F6525/6621/8525/8621
—
—
—
—
—
—
—
—
—
—
WDTPS3 WDTPS2 WDTPS1
REV4
DEV7
Bit 4
—
—
—
—
—
—
—
—
—
—
—
EBTR3
WRT3
BORV1
FOSC3
CP3
REV3
DEV6
Sleep mode is designed to offer a very low current
power-down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost, while the
LP crystal option saves power. A set of configuration
bits is used to select various options.
24.1
The configuration bits can be programmed (read as ‘0’)
or left unprogrammed (read as ‘1’), to select various
device configurations. These bits are mapped, starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration
3FFFFFh) which can only be accessed using table
reads and table writes.
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
EECON1 register WR bit starts a self-timed write to the
Configuration register. In normal operation mode, a
TBLWT instruction, with the TBLPTR pointed to the
Configuration register, sets up the address and the
data for the Configuration register write. Setting the WR
bit starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT instruction
can write a ‘1’ or a ‘0’ into the cell.
Bit 3
—
—
—
—
—
—
(2)
(2)
(2)
BORV0
FOSC2
EBTR2
WRT2
REV2
DEV5
Configuration Bits
Bit 2
LVP
CP2
—
—
—
—
—
memory
ECCPMX
WDTPS0
FOSC1
EBTR1
WRT1
REV1
DEV4
Bit 1
BOR
PM1
CP1
—
—
—
—
(1)
space
PWRTEN
CCP2MX
STVREN
WDTEN
FOSC0
EBTR0
WRT0
REV0
DEV3
Bit 0
PM0
CP0
—
—
—
(300000h
DS39612B-page 259
Unprogrammed
--1- 1111
---- 1111
---1 1111
1--- --11
1--- --11
1--- -1-1
---- 1111
11-- ----
---- 1111
111- ----
---- 1111
-1-- ----
0000 1010
(Note 3)
Default/
Value
through