PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 28

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F6525/6621/8525/8621
2.6.2
PIC18F6525/6621/8525/8621 devices contain circuitry
to prevent “glitches” when switching between oscillator
sources. Essentially, the circuitry waits for eight rising
edges of the clock source that the processor is switch-
ing to. This ensures that the new clock source is stable
and that its pulse width will not be less than the shortest
pulse width of the two clock sources.
FIGURE 2-8:
The sequence of events that takes place when switch-
ing from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
FIGURE 2-9:
DS39612B-page 26
(OSCCON<0>)
Note:
(OSCCON<0>)
System Clock
Note: T
Program
Counter
Internal
System
Program
T1OSI
OSC1
Counter
Clock
Internal
SCS
T1OSI
T
OSC1
DLY
SCS
OSCILLATOR TRANSITIONS
OST
is the delay from SCS high to first count of transition circuit.
Q1
= 1024 T
T
OSC
Q2
Q3
PC
Q3
PC
OSC
TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
Q4
Q4
(drawing not to scale).
Q1
T
DLY
1
Q1
2
T
T
1
P
3
T
OST
4
T
PC + 2
SCS
T
OSC
5
6
PC + 2
A timing diagram indicating the transition from the main
oscillator to the Timer1 oscillator is shown in Figure 2-8.
The Timer1 oscillator is assumed to be running all the
time. After the SCS0 bit is set, the processor is frozen at
the next occurring Q1 cycle. After eight synchronization
cycles are counted from the Timer1 oscillator, operation
resumes. No additional delays are required after the
synchronization cycles.
If the main oscillator is configured for an external
crystal (HS, XT, LP), then the transition will take place
after an oscillator start-up time (T
timing diagram, indicating the transition from the
Timer1 oscillator to the main oscillator for HS, XT and
LP modes, is shown in Figure 2-9.
1
7
2
8
Q1
3
4
Q2
T
T
SCS
T
1
5
P
Q3
6
 2005 Microchip Technology Inc.
Q4
7
Q1 Q2 Q3 Q4 Q1 Q2
8
Q1
OST
Q2
PC + 4
) has occurred. A
Q3
PC + 6
Q4
Q3
Q1