ispPAC-POWR1014-01T48I Lattice, ispPAC-POWR1014-01T48I Datasheet - Page 14

• Manufacturer Part Number: ispPAC-POWR1014-01T48I
• Description: Supervisory Circuits Prec. Prog. Pwr Sppl y Seq. Mon. Trim I
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of ispPAC-POWR1014-01T48I

• Number Of Voltages Monitored: 10
• Output Type: Open Collector / Drain
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Power-up Reset Delay (typ): 500 ms
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 20 mA
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Applications: General Purpose
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 20mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-7. ispPAC-POWR1014/A Voltage Monitors
Figure 2-7 shows the functional block diagram of one of the 10 voltage monitor inputs - ‘x’ (where x = 1...10). Each
voltage monitor can be divided into three sections: Analog Input, Window Control, and Filtering.
The voltage input is monitored by two individually programmable trip-point comparators, shown as CompA and
CompB. Table 2-1 shows all trip points and the range to which any comparator’s threshold can be set.
Each comparator outputs a HIGH signal to the PLD array if the voltage at its positive terminal is greater than its pro-
grammed trip point setting, otherwise it outputs a LOW signal.
A hysteresis of approximately 1% of the setpoint is provided by the comparators to reduce false triggering as a
result of input noise. The hysteresis provided by the voltage monitor is a function of the input divider setting.
Table 2-3 lists the typical hysteresis versus voltage monitor trip-point.
AGOOD Logic Signal
All the VMON comparators auto-calibrate immediately after a power-on reset event. During this time, the digital
glitch filters are also initialized. This process completion is signalled by an internally generated logic signal:
AGOOD. All logic using the VMON comparator logic signals must wait for the AGOOD signal to become active.
Programmable Over-Voltage and Under-Voltage Thresholds
Figure 2-8 (a) shows the power supply ramp-up and ramp-down voltage waveforms. Because of hysteresis, the
comparator outputs change state at different thresholds depending on the direction of excursion of the monitored
power supply.
VMONx
Trip Point A
Trip Point B
Analog Input
+
–
+
–
ispPAC-POWR1014/A
Comp A
Comp B
2-14
Window Control
Comp A/Window
Select
ispPAC-POWR1014/A Data Sheet
Glitch
Glitch
Filter
Filter
Filtering
VMONxA
Signal
Logic
VMONxB
Signal
Logic
Unit (POWR1014A
JTAG Interface
VMONx Status
I
2
C Interface/
To ADC
(POWR1014A only)
only)
Array
PLD