ispPAC-POWR1014-01T48I Lattice, ispPAC-POWR1014-01T48I Datasheet - Page 42

• Manufacturer Part Number: ispPAC-POWR1014-01T48I
• Description: Supervisory Circuits Prec. Prog. Pwr Sppl y Seq. Mon. Trim I
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of ispPAC-POWR1014-01T48I

• Number Of Voltages Monitored: 10
• Output Type: Open Collector / Drain
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Power-up Reset Delay (typ): 500 ms
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 20 mA
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Applications: General Purpose
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 20mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-34. UES Register
UES_PROGRAM – This instruction will program the content of the UES Register into the UES E
The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces
the outputs into the OUTPUTS_HIGHZ.
ERASE_DONE_BIT – This instruction clears the 'Done' bit, which prevents the ispPAC-POWR1014/A sequence
from starting.
PROGRAM_DONE_BIT – This instruction sets the 'Done' bit, which enables the ispPAC-POWR1014/A sequence
to start.
RESET – This instruction resets the PLD sequence and output macrocells.
IN1_RESET_JTAG_BIT – This instruction clears the JTAG Register logic input 'IN1.' The PLD input has to be con-
figured to take input from the JTAG Register in order for this command to have effect on the sequence.
IN1_SET_JTAG_BIT – This instruction sets the JTAG Register logic input 'IN1.' The PLD input has to be config-
ured to take input from the JTAG Register in order for this command to have effect on the sequence.
PLD_VERIFY_INCR – This instruction reads out the PLD data register for the current address and increments the
address register for the next read.
Notes:
In all of the descriptions above, OUTPUTS_HIGHZ refers both to the instruction and the state of the digital output
pins, in which the open-drains are tri-stated and the FET drivers are pulled low.
Before any of the above programming instructions are executed, the respective E
using the corresponding erase instruction.
Accessing I
I
JTAG command codes shown in Table 2-12.
Note: The SCL pin of the I
accessed via the JTAG port.
Table 2-12. JTAG Command Codes
There are 12 bits in the I2C_Control_Register and 72 bits in the I2C_Data_Register packet. All I
tents, except the UES bits, can be read out through the 72-bit I2C_Data_Register packet. All I
be written by shifting in a 72-bit I2C_Data_Register packet. The I2C_Control_Register bits are used to select the
I
The reading (shifting out) and writing (shifting in) of I2C_Data_Register and writing of the I2C_Control_Register
through the JTAG port follows the TAP states protocol shown in Figure 2-31.
I2C_DATA_REGISTER
I2C_CONTROL_REGISTER
2
2
C registers can be read or written through the JTAG interface of the ispPAC-POWR1014A devices using the two
C registers read as well as written.
Bit
15
Instruction
Bit
14
Bit
13
2
C Registers through JTAG (ispPAC-POWR1014A Only)
Bit
12
2
C port should be pulled high during the entire time that the I
Bit
11
Command Code
0010 0110
0010 0101
Bit
10
Bit
9
Accessing I
Controls Read and Write Functions of I
Bit
8
2-42
Bit
7
2
C Data Register Through JTAG (72 Bits)
Bit
6
Bit
5
ispPAC-POWR1014/A Data Sheet
Comments
Bit
4
2
Bit
3
CMOS bits need to be erased
2
C Registers (12 Bits)
Bit
2
2
C registers are being
2
C write registers can
Bit
1
2
CMOS memory.
2
C register con-
Bit
0
TDO