ispPAC-POWR1014-01T48I Lattice, ispPAC-POWR1014-01T48I Datasheet - Page 29

• Manufacturer Part Number: ispPAC-POWR1014-01T48I
• Description: Supervisory Circuits Prec. Prog. Pwr Sppl y Seq. Mon. Trim I
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of ispPAC-POWR1014-01T48I

• Number Of Voltages Monitored: 10
• Output Type: Open Collector / Drain
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Power-up Reset Delay (typ): 500 ms
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 20 mA
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Applications: General Purpose
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 20mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
command (Waiting for the DONE bit to be set to 1). An alternative would be to wait for a minimum specified time
(see T
Note that if the I
conversion is to wait the minimum specified time (T
than that cannot be guaranteed. In other words, if the I
not assert even though a valid conversion result is available.
To insure every ADC conversion result is valid, preferred operation is to clock I
DONE bit status or wait for the full T
request is placed before the current conversion is complete, the DONE bit will be set to 1 only after the second
request is complete.
The status of the digital input lines may also be monitored and controlled through I
shows the I
INPUT_STATUS register, while input values to the PLD array may be set by writing to the INPUT_VALUE register.
To be able to set an input value for the PLD array, the input multiplexer associated with that bit needs to be set to
the I
Figure 2-20. I
The digital outputs may also be monitored and controlled through the I
status of any given digital output may be read by reading the contents of the associated OUTPUT_STATUS[1:0]
register. Note that in the case of the outputs, the status reflected by these registers reflects the logic signal used to
drive the pin, and does not sample the actual level present on the output pin. For example, if an output is set high
2
C register setting in E
CONVERT
2
C interface to the IN[1:4] digital input lines. The input status may be monitored by reading the
2
C Digital Input Interface
value in the specifications) and disregard checking the DONE bit.
2
C clock rate falls below 50kHz (see F
0x11 - INPUT_VALUE (Read/Write)
0x06 - INPUT_STATUS (Read Only)
2
IN[2..4]
b7
b7
X
CMOS memory otherwise the PLD will receive its input from the INx pin.
1
IN1
USERJTAG
b6
b6
X
1
CONVERT
Bit
Input_Value
b5
b5
PLD Output/Input_Value Register Select
1
X
3
3
time period between subsequent ADC convert commands. If an I
I
2
CONVERT
C Interface Unit
b4
b4
MUX
MUX
1
X
(E 2 Configuration)
I 2 C
2-29
2
C clock rate is less than 50kHz, the DONE bit may or may
note in specifications), the only way to insure a valid ADC
3
2
IN4
), as the operation of the DONE bit at clock rates lower
b3
b3
I4
Input_Status
3
IN3
b2
b2
I3
2
ispPAC-POWR1014/A Data Sheet
C interface, as shown in Figure 2-21. The
IN2
b1
b1
I2
2
C at more than 50kHz and verify
Array
PLD
IN1
b0
b0
X
2
C commands. Figure 2-20
2
C