ispPAC-POWR1014-01T48I Lattice, ispPAC-POWR1014-01T48I Datasheet - Page 32

• Manufacturer Part Number: ispPAC-POWR1014-01T48I
• Description: Supervisory Circuits Prec. Prog. Pwr Sppl y Seq. Mon. Trim I
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of ispPAC-POWR1014-01T48I

• Number Of Voltages Monitored: 10
• Output Type: Open Collector / Drain
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Power-up Reset Delay (typ): 500 ms
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 20 mA
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Applications: General Purpose
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 20mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
SMBus SMBAlert Function
The ispPAC-POWR1014A provides an SMBus SMBAlert function so that it can request service from the bus mas-
ter when it is used as part of an SMBus system. This feature is supported as an alternate function of OUT3. When
the SMBAlert feature is enabled, OUT3 is controlled by a combination of the PLD output and the GP3_ENb bit
(Figure 2-24). Note: To enable the SMBAlert feature, the SMB_Mode (EECMOS bit) should be set in software.
Figure 2-24. ispPAC-POWR1014/A SMBAlert Logic
The typical flow for an SMBAlert transaction is as follows (Figure 2-24):
Figure 2-25. SMBAlert Bus Transaction
After OUT3/SMBA has been released, the bus master (typically a microcontroller) may opt to perform some service
functions in which it may send data to or read data from the ispPAC-POWR1014A. As part of the service functions,
the bus master will typically need to clear whatever condition initiated the SMBAlert request, and will also need to
reset GP3_ENb to re-enable the SMBAlert function. For further information on the SMBus, the user should consult
the SMBus Standard.
SMBA
1. GP3_ENb bit is forced (Via I
2. ispPAC-POWR1014A PLD Logic pulls OUT3/SMBA Low
3. Master responds to interrupt from SMBA line
4. Master broadcasts a read operation using the SMBus Alert Response Address (ARA)
5. ispPAC-POWR1014A responds to read request by transmitting its device address
6. If transmitted device address matches ispPAC-POWR1014A address, it sets GP3_ENb bit high. 
SDA
SCL
This releases OUT3/SMBA.
ASSERTS
SLAVE
SMBA
Routing
Output
Pool
PLD
START
I 2 C Interface Unit
PLD Output/GP_Output Register Select
0
1
GP3_ENb
0
2
(E 2 Configuration)
2
ALERT RESPONSE ADDRESS
C write) to Low
0
3
MUX
1
4
(0001 100)
1
5
0
6
7
0
R/W
SMBAlert
8
2-32
Logic
OUT3/SMBA Mode Select
ACK
9
(E 2 Configuration)
A6
1
MUX
A5
2
ispPAC-POWR1014/A Data Sheet
A4
SLAVE ADDRESS (7 BITS)
3
A3
4
A2
5
A1
6
OUT3/SMBA
A0
7
Note: Shaded Bits Asserted by Slave
8
x
ACK
9
RELEASES
SLAVE
SMBA
STOP