ispPAC-POWR1014-01T48I Lattice, ispPAC-POWR1014-01T48I Datasheet - Page 28

Supervisory Circuits Prec. Prog. Pwr Sppl y Seq. Mon. Trim I

ispPAC-POWR1014-01T48I

Manufacturer Part Number
ispPAC-POWR1014-01T48I
Description
Supervisory Circuits Prec. Prog. Pwr Sppl y Seq. Mon. Trim I
Manufacturer
Lattice
Series
ispPAC®r

Specifications of ispPAC-POWR1014-01T48I

Number Of Voltages Monitored
10
Output Type
Open Collector / Drain
Manual Reset
Not Resettable
Watchdog
No Watchdog
Power-up Reset Delay (typ)
500 ms
Supply Voltage (max)
3.96 V
Supply Voltage (min)
2.8 V
Supply Current (typ)
20 mA
Mounting Style
SMD/SMT
Package / Case
TQFP-48
Applications
General Purpose
Voltage - Input
-0.3 V ~ 5.9 V
Voltage - Supply
2.8 V ~ 3.96 V
Current - Supply
20mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISPPAC-POWR1014-01T48I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
ISPPAC-POWR1014-01T48I
Manufacturer:
LATTICE
Quantity:
790
Part Number:
ISPPAC-POWR1014-01T48I
Manufacturer:
LATTICE
Quantity:
20 000
Lattice Semiconductor
Figure 2-19. ADC Interface Registers
To perform an A/D conversion, one must set the input attenuator and channel selector. Two input ranges may be
set using the attenuator, 0 - 2.048V and 0 - 6.144V. Table 2-8 shows the input attenuator settings.
Table 2-8. ADC Input Attenuator Control
The input selector may be set to monitor any one of the ten VMON inputs, the VCCA input, or the VCCINP input.
Table 2-9 shows the codes associated with each input selection.
Table 2-9. V
Writing a value to the ADC_MUX register to set the input attenuator and selector will automatically initiate a conver-
sion. When the conversion is in process, the DONE bit (ADC_VALUE_LOW.0) will be reset to 0. When the conver-
sion is complete, this bit will be set to 1. When the conversion is complete, the result may be read out of the ADC by
performing two I
mended that the I
MON
2
Address Selection Table
2
C read operations; one for ADC_VALUE_LOW, and one for ADC_VALUE_HIGH. It is recom-
(ADC_MUX.3)
C master load a second conversion command only after the completion of the current conversion
0x07 - ADC_VALUE_LOW (Read Only)
0x08 - ADC_VALUE_HIGH (Read Only)
0x09 - ADC_MUX (Read/Write)
SEL3
D11
D3
ATTEN (ADC_MUX.4)
b7
b7
b7
X
0
0
0
0
0
0
0
0
1
1
1
1
D10
D2
0
1
b6
b6
b6
X
(ADC_MUX.2)
SEL2
0
0
0
0
1
1
1
1
0
0
1
1
D1
D9
b5
b5
b5
X
Select Word
ATTEN
(ADC_MUX.1)
D0
D8
b4
b4
b4
Resolution
SEL1
2-28
2mV
6mV
0
0
1
1
0
0
1
1
0
0
0
0
SEL3
D7
b3
b3
b3
1
(ADC_MUX.0)
SEL2
D6
b2
b2
b2
1
SEL0
ispPAC-POWR1014/A Data Sheet
0
1
0
1
0
1
0
1
0
1
0
1
Full-Scale Range
2.048 V
6.144 V
SEL1
D5
b1
b1
b1
1
Input Channel
VMON10
VCCINP
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
VCCA
DONE
SEL0
D4
b0
b0
b0

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